Signal transmission circuit capable of tolerating high-voltage input signal

A signal transmission circuit comprising:

• a first transmission circuit for transmitting a signal of a first node to a second node, the first transmission circuit being a first NMOS transistor, a first supply voltage being input to the gate of the first NMOS transistor, a first end of the first NMOS transistor being connected to the first node, and a second end of the first NMOS transistor being connected to the second node;
• a second transmission circuit for transmitting the signal of the first node to the second node;
• an inverting circuit for inverting the signal of the second node;
• a first switching circuit for pulling down a third node in response to an output signal of the inverting circuit;
• and
• a second switching circuit for transmitting the signal of the first node to the third node;
• wherein the second transmission circuit is controlled in response to the signal of the third node;
• wherein the second transmission circuit is a first PMOS transistor, a gate of the first PMOS transistor is connected to the third node, a first end of the first PMOS transistor is connected to the first node, and a second end of the first PMOS transistor is connected to the second node;
• wherein the first switching circuit includes a second NMOS transistor, an output signal of the inverting circuit is input to the gate of the second NMOS transistor, a first end of the second NMOS transistor is connected to the ground voltage, and a second end of the second NMOS transistor is connected to the third node;
• wherein the second switching circuit is a second PMOS transistor, a second supply voltage is input to the gate of the second PMOS transistor, a first end of the second PMOS transistor is connected to the first node, and a second end of the second PMOS transistor is connected to the third node;
• and wherein the first and second supply voltages are not equal.