US 6,724,224 B1Granted

Bus relay and voltage shifter without direction control input

AssigneePericom Semiconductor Corp.

InventorXianxin Li

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Abstract

A bi-directional bus-interface chip has no direction-control input. A forward buffer and a reverse buffer are both normally disabled in the high-impedance state. When a transition occurs on one input bus, a driver transistor in the forward or reverse buffer is activated to pass the transition through the bus-interface chip. After a delay, the driver transistor is disabled. An optional bus-hold circuit maintains voltage levels on buses when driver transistors are disabled. The delay can be selectable by shorting delay resistors in the delay circuit. The high-level voltages on the two busses may differ. The bus-interface chip converts one voltage domain to another and can re-generate weak signals. A pre-buffer may be added to gradually step up the voltage level when differences in voltage domains are large.

Claims20

Dependent claims

A bus-interface chip without a direction-control input comprising:

a plurality of bit slices between bits of a first bus and corresponding bits of a second bus, each bit slice comprising:
a forward buffer having an input coupled to a first bus line that is a bit of the first bus and an output for driving a second bus line that is a bit of the second bus;
a first delay, coupled to the first bus line, for generating a first delayed signal after a delay from a transition on the first bus line;
the forward buffer being enabled to drive the second bus line in response to the transition on the first bus line, the forward buffer being disabled from driving the second bus line in response to the first delayed signal;
a reverse buffer having an input coupled to the second bus line and an output for driving the first bus line;
and
a second delay, coupled to the second bus line, for generating a second delayed signal after a delay from a transition on the second bus line;
the reverse buffer being enabled to drive the first bus line in response to the transition on the second bus line, the reverse buffer being disabled from driving the first bus line in response to the second delayed signal,
whereby the forward buffer and the reverse buffer are enabled and disabled without using a direction-control input to the bus-interface chip.

6 more elements

A bi-directional interface circuit comprising:

a first bi-directional input;
a second bi-directional input;
a first delay circuit, coupled to the first bi-directional input, for generating a first delay signal having delayed transitions after a delay from transitions of the first bi-directional input;
a forward buffer comprising:
a forward NAND gate, coupled to the first bi-directional input and to the first delay signal, for generating a forward p-gate signal;
a forward p-channel driver transistor, driven by the forward p-gate signal, for driving the second bi-directional input high;
a forward NOR gate, coupled to the first bi-directional input and to the first delay signal, for generating a forward n-gate signal;
a forward n-channel driver transistor, driven by the forward n-gate signal, for driving the second bi-directional input low;
a second delay circuit, coupled to the second bi-directional input, for generating a second delay signal having delayed transitions after a delay from transitions of the second bi-directional input;
a reverse buffer comprising:
a reverse NAND gate, coupled to the second bi-directional input and to the second delay signal, for generating a reverse p-gate signal;
a reverse p-channel driver transistor, driven by the reverse p-gate signal, for driving the first bi-directional input high;
a reverse NOR gate, coupled to the second bi-directional input and to the second delay signal, for generating a reverse n-gate signal;
a reverse n-channel driver transistor, driven by the reverse n-gate signal, for driving the first bi-directional input low.

11 more elements

A bus relay comprising:

a first input and a second input;
first delay means for delaying transitions on the first input to generate a first delayed input;
forward buffer means, coupled to the first input and to the first delayed input, for driving the second input high to a second voltage immediately after the first input transitions high and before the first delayed input transitions in response to the first input transitioning high, and for driving the second input low to a ground voltage immediately after the first input transitions low and before the first delayed input transitions in response to the first input transitioning low;
second delay means for delaying transitions on the second input to generate a second delayed input;
and
reverse buffer means, coupled to the second input and to the second delayed input, for driving the first input high to a first voltage immediately after the second input transitions high and before the second delayed input transitions in response to the second input transitioning high, and for driving the first input low to a ground voltage immediately after the second input transitions low and before the second delayed input transitions in response to the second input transitioning low,
whereby the first and second input are bi-directionally buffered without a direction-control input.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/249,413Filed 7 Apr 2003
Granted: 20 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H04L 5/16
Two-way operation using the same type of signal, i.e. duplex: half-duplex systems; Simplex/duplex switching; Transmission of break signals…
H03K 19/018521
Interface arrangements: of complementary type, e.g. CMOS
H03K 19/018592
Using field effect transistors only: with a bidirectional operation
H03K 2005/00058
Variable delay: controlled by a digital setting

Family

No related US applications are recorded in the indexed filing history.

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