Semiconductor device having a wiring pattern and method for manufacturing the same
AssigneeSeiko Epson Corporation
InventorToshihiko Higuchi
Life of this patent
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Abstract
A semiconductor device has a wiring pattern formed by etching a conductive layer using a resist pattern as a mask. The semiconductor device includes a contact section and a wiring. The contact section is formed in an interlayer dielectric layer. The wiring has a connection region to be connected to the contact section. The connection region of the wiring has a generally square plan configuration. The wiring has an extension section extending in a non-wiring region in the connection region.
Claims27
A semiconductor device having a wiring pattern that is formed by etching a conductive layer using a resist pattern as a mask, the semiconductor device comprising:
- a contact section formed in an interlayer dielectric layer;
- a first wiring formed over the interlayer dielectric layer and disposed with a separation from the contact section shorter than a predetermined separation;
- and
- a second wiring having a connection region connected to the contact section,
- wherein the second wiring has an extension section, which extends from a side of the connection region in a non-wiring region, and
- the extension section extends from at least one section of the connection region other than sides of the connection region facing the first wiring, wherein the extension section does not extend from the side of the connection region facing the first wiring.
A semiconductor device having a wiring pattern formed by etching a conductive layer using a resist pattern as a mask, the semiconductor device comprising:
- a contact section formed in an interlayer dielectric layer;
- a first wiring formed over the interlayer dielectric layer and disposed with a predetermined inter-wiring separation with respect to the contact section;
- and
- a second wiring having a connection region to be connected to the contact section and extending in parallel with the first wiring,
- wherein the connection region of the second wiring has a generally square plan configuration,
- the second wiring has an extension section extending in a non-wiring region in the connection region, and
- the extension section does not extend from sides of the connection region facing the first wiring.
A semiconductor device having a wiring pattern formed by etching a conductive layer using a resist pattern as a mask, the semiconductor device comprising:
- a contact section formed in an interlayer dielectric layer;
- a first wiring formed over the interlayer dielectric layer and disposed with a predetermined inter-wiring separation with respect to the contact section;
- and
- a second wiring having a connection region to be connected to the contact section and extending in a direction perpendicular to the first wiring,
- wherein the connection region of the second wiring has a generally square plan configuration,
- the second wiring has an extension section extending in a non-wiring region in the connection region, and
- the extension section does not extend from a sides of the connection region facing the first wiring.
A semiconductor device having a wiring pattern formed by etching a conductive layer using a resist pattern as a mask, the semiconductor device comprising:
- a contact section formed in an interlayer dielectric layer;
- a first wiring formed over the interlayer dielectric layer and disposed with a predetermined inter-wiring separation with respect to the contact section;
- and
- a second wiring having a connection region to be connected to the contact section and having a section extending in parallel with the first wiring and a section extending in a direction perpendicular to the first wiring,
- wherein the connection region of the second wiring has a generally square plan configuration,
- the second wiring has an extension section extending in a non-wiring region in the connection region, and
- the extension section does not extend from a sides of the connection region facing the first wiring.
A semiconductor device having a wiring pattern formed by etching a conductive layer using a resist pattern as a mask, the semiconductor device comprising:
- a contact section formed in an interlayer dielectric layer;
- a first wiring formed over the interlayer dielectric layer and disposed with a predetermined inter-wiring separation with respect to the contact section;
- and
- a second wiring having only a connection region to be connected to the contact section,
- wherein the connection region of the second wiring has a generally square plan configuration,
- the second wiring has an extension section extending in a non-wiring region in the connection region;
- and
- the extension section does not extend from a sides of the connection region facing the first wiring.
A semiconductor device having a wiring pattern formed by etching a conductive layer using a resist pattern as a mask, the semiconductor device comprising:
- a contact section formed in an interlayer dielectric layer;
- a plurality of first wirings formed over the interlayer dielectric layer and disposed with a predetermined inter-wiring separation with respect to the contact section;
- and
- a second wiring having at least one connection region to be connected to the contact section,
- wherein the connection region of the second wiring has a generally square plan configuration,
- the second wiring has an extension section extending in a non-wiring region in the connection region, and
- the extension section does not extend from a sides of the connection region facing the plurality of first wirings.
A semiconductor device having a wiring pattern formed by etching a conductive layer using a resist pattern as a mask, the semiconductor device comprising:
- a contact section formed in an interlayer dielectric layer;
- and
- a wiring having a connection region to be connected to the contact section,
- wherein the connection region of the wiring has a generally square plan configuration, and
- the wiring has an extension section extending in a non-wiring region in the connection region, and
- the extension section does not extend from a side of the connection region facing the plurality of first wirings.
Dependencies are inferred from the claim text.