Semiconductor package having multi-signal bus bars

A semiconductor package comprising:

• a semiconductor die having a computer processor;
• a plurality of die-side contact pads;
• a plurality of board-side contact pads;
• a substrate base having a plurality of traces and vias interconnecting the die-side contact pads and the board-side contact pads;
• a first dielectric member;
• an electrically conductive reference member coupled to a first surface of the first dielectric member, the reference member defining a current path for a reference signal;
• a first plurality of electrically conductive I/O members coupled to a second surface of the first dielectric member through a first dielectric layer, the first I/O members defining current paths for a corresponding first plurality of I/O signals;
• a second dielectric member having a first surface coupled to the reference member, the dielectric members being positioned on opposite sides of the reference member;
• and
• a second plurality of electrically conductive I/O members coupled to a second surface of the second dielectric member, the second I/O members defining current paths for a corresponding second plurality of I/O signals, the dielectric members and the I/O members defining a multi-signal bus bar extending from a board side of the semiconductor package, wherein the I/O members have a predetermined spacing, the I/O members being electrically isolated from one another;
• and a second dielectric layer disposed between the second dielectric member and the second I/O members.