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US 6,724,055 B2Granted
Semiconductor structure having an interconnect and method of producing the semiconductor structure
AssigneeInfineon Technologies AG
InventorGerd Lichter
Life of this patent
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Abstract
The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.
Claims9
A semiconductor structure in an integrated circuit, comprising:
- an insulating layer on a support;
- an interconnect above said insulating layer and separated by a cavity from said insulating layer;
- an insulating covering laterally adjoining, in the form of a spacer, said interconnect, said cavity and an upper surface of said interconnect;
- said covering having an opening formed therein, extending beyond said interconnect on one side of said interconnect;
- and
- a further insulation layer covering said covering and said opening.
3 more elements
Dependencies are inferred from the claim text.