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US 6,724,041 B2Granted
Method of making a high-voltage transistor with buried conduction regions
AssigneePower Integrations, Inc.
InventorsVladimir Rumennik, Donald R. Disney, Janardhanan S. Ajit
Life of this patent
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Abstract
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.
Claims20
A high voltage field-effect transistor (HVFET) comprising:
- a substrate of a first conductivity type;
- a source diffusion region of a second conductivity type opposite to the first conductivity type disposed in the substrate, the source diffusion region having a source fingertip area;
- a first region of the second conductivity type disposed in the substrate inter-digitated with the source diffusion region, the first region being separated in a lateral direction from the source diffusion region by a channel region;
- a drain diffusion region of the second conductivity type disposed in the first region;
- a drain electrode electrically connected to the drain diffusion region;
- a buffer region of the substrate separating the source diffusion region from the first region adjacent the source fingertip area, the buffer region being substantially wider than the channel region, the first region extending laterally beyond the drain electrode adjacent the buffer region;
- an insulated gate disposed above the channel region;
- a source electrode electrically connected to the source diffusion region;
- a buried region of the first conductivity type disposed within the first region, a first conduction channel being formed above the buried region and a second conduction channel being formed below the buried region.
6 more elements
A high voltage field-effect transistor (HVFET) comprising:
- a substrate of a first conductivity type;
- a source diffusion region of a second conductivity type opposite to the first conductivity type disposed in the substrate, the source diffusion region having a source fingertip area;
- a first region of the second conductivity type disposed in the substrate inter-digitated with the source diffusion region, the first region being separated in a lateral direction from the source diffusion region by a channel region, the first region being separated from the source fingertip area by a buffer region that is substantially wider than the channel region;
- a drain diffusion region of the second conductivity type disposed in the first region;
- a drain electrode electrically connected to the drain diffusion region;
- insulated gate disposed above the channel region;
- a source electrode electrically connected to the source diffusion region;
- a buried region of the first conductivity type disposed within the first region, the buried region forming JFET channels within the first region, one JFET channel being formed above the buried region with a doped impurity concentration of approximately 1×1012/cm2 or greater and another JFET channel below the buried region.
5 more elements
A high voltage field-effect transistor (HVFET) comprising:
- a substrate of a first conductivity type;
- a source diffusion region of a second conductivity type opposite to the first conductivity type disposed in the substrate, the source diffusion region having a source fingertip area;
- a first region of the second conductivity type disposed in the substrate inter-digitated with the source diffusion region, the first region being separated in a lateral direction from the source diffusion region by a channel region;
- a drain diffusion region of the second conductivity type disposed in the first region;
- a drain electrode electrically connected to the drain diffusion region;
- a buffer region of the substrate separating the source diffusion region from the first region adjacent the source fingertip area, the buffer region being substantially wider than the channel region;
- an insulated gate disposed above the channel region;
- a source electrode electrically connected to the source diffusion region;
- a buried region of the first conductivity type disposed within the first region, a first conduction channel being formed above the buried region and a second conduction channel being formed below the buried region, the first conduction channel being approximately 0.5 to 1.5 microns thick.
6 more elements
Dependencies are inferred from the claim text.