Method for preventing strap-to-strap punch through in vertical DRAMs

A method of fabricating a dynamic random access memory cell comprising:

• providing a trench capacitor formed in a silicon substrate;
• providing a vertical metal-oxide-silicon field effect transistor formed in said silicon substrate above said trench capacitor, said vertical metal-oxide-silicon field effect transistor having a gate electrode, a first source/drain region extending from a surface of said silicon substrate into said silicon substrate, a buried second source/drain region electrically contacting said trench capacitor, a channel region formed in said silicon substrate between said first source/drain region and said buried second source/drain region and a gate oxide layer disposed between said gate electrode and said channel region;
• said first source/drain region also belonging to an adjacent vertical metal-oxide-silicon field effect transistor, said adjacent vertical metal-oxide-silicon field effect transistor having a buried third source/drain region electrically connected to an adjacent trench capacitor, said buried second and third source/drain regions extending toward one another, and
• forming a punch through prevention region disposed between said buried second and third source/drain regions.

A method of fabricating a dynamic random access memory cell comprising:

• providing a trench capacitor formed in a silicon substrate;
• providing a vertical metal-oxide-silicon field effect transistor formed in a silicon substrate above said trench capacitor, said vertical metal-oxide-silicon field effect transistor having a gate electrode, a first source/drain region extending from a surface of said silicon substrate into said silicon substrate, a buried second source/drain region electrically contacting said trench capacitor, a channel region formed in said silicon substrate between said first source/drain region and said buried second source/drain region and a gate oxide layer disposed between said gate lecode and said channel region;
• said first source/drain region also belonging to an adjacent vertical metal-oxide-silicon field effect transistor, said adjacent vertical metal-oxide-silicon field effect transistor having a buried third source/drain region electrically connected to an adjacent trench capacitor, said buried second and third source/drain regions extending toward one another;
• forming a blocking layer over ad surface of said silicon substrate;
• forming a trench in said blocking layer, said trench aligned between said vertical metal-oxide-silicon field effect transistor and said adjacent said vertical metal-oxide-silicon field effect transistor;
• and
• performing an ion implantation to form a punch through prevention region in said silicon substrate aligned under said trench and disposed between said buried second and third source/drain regions, said blocking layer blocking said ion implantation from reaching said silicon substrate.