Method for controlling and monitoring a chemical mechanical polishing process
AssigneeMacronix International Co., Ltd.
InventorsChun-Lien Su, Chi-Yuan Chin, Shih-Keng Cho, Ming-Shang Chen, Yih-Shi Lin
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Abstract
The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.
Claims10
A method of determining proper process time of chemical mechanical polishing, the method comprising:
- forming a film on a wafer having at least one device region and at least one test region;
- calculating a first pattern density of the device region to determine a second pattern density of the test region such that the second pattern density is substantially compatible with the first pattern density;
- patterning the film on the wafer to form a first pattern, having the first pattern density, on the device region and a second pattern, having the second pattern density, on the test region to form dummy structures on the substrate;
- and
- polishing the film on the wafer by chemical mechanical polishing until a thickness of the film on the test region is zero.
A method of forming shallow trench isolation, the method comprising:
- forming a first dielectric layer on a wafer having at least one device region and at least one test region;
- etching the first dielectric layer and the wafer to form at least one trench on the device region;
- forming a second dielectric layer on the wafer and in the trench to fill the trench;
- calculating a first pattern density of the device region to determine a second pattern density of the test region such that the second pattern density is substantially compatible with the first pattern density;
- etching the second dielectric layer on the wafer to form a first pattern, having the first pattern density, on the device region and a second pattern, having the second pattern density, on the test region until the first dielectric layer is exposed, and transforming the second dielectric layer to dummy structures on the substrate;
- and
- polishing the second dielectric layer on the wafer by chemical mechanical polishing until a thickness of the second dielectric layer on the test region is zero to form shallow trench isolation in the trench.
Dependencies are inferred from the claim text.