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US 6,723,635 B1Granted
Protection low-k ILD during damascene processing with thin liner
AssigneeAdvanced Micro Devices, Inc.
InventorsMinh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Jr., Suzette K. Pangrle
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Abstract
Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
Claims15
A method of manufacturing a semiconductor device, the method comprising:
- forming a dielectric layer having an upper surface over a conductive feature;
- forming an opening in the dielectric layer exposing an upper surface of the conductive feature;
- forming a silicon carbide layer, having an upper silicon surface, lining the opening;
- depositing a barrier layer on the upper silicon surface of the silicon carbide layer;
- and
- filling the opening with copper (Cu) or a Cu alloy.
3 more elements
Dependencies are inferred from the claim text.