Interconnect exhibiting reduced parasitic capacitance variation

A process for forming an interconnect, the process comprising:

• forming a lower interlayer dielectric over a semiconductor workpiece;
• patterning a photoresist mask over the lower interlayer dielectric, the photoresist including a masked region having a critical dimension and excluding an unmasked region;
• etching the interlayer dielectric in the unmasked region to leave a first trench separated from a second trench by an inter-line region composed of the first interlayer dielectric, a width of the first and second trenches corresponding to the critical dimension;
• forming an interconnect metallization layer over the lower interlayer dielectric and within the first and second trenches;
• removing the interconnect metallization layer outside of the first and second trenches to leave a first metal line occupying the first trench and a second metal line occupying the second trench, the first and second metal lines exhibiting a parasitic capacitance;
• removing the first interlayer dielectric in the inter-line region;
• forming a conformal middle interlayer dielectric over the first and second metal lines and within the inter-line region;
• and
• forming a third metal line over the conformal middle interlayer dielectric, the third metal line electronically linked with the first metal line and projecting between the first and second metal lines in the inter-line region to elevate the parasitic capacitance and thereby reduce an overall variation in parasitic capacitance;
• and
• wherein the interconnect metallization layer has a thickness, and wherein the step of forming the middle interlayer dielectric comprises forming the middle interlayer dielectric with a thickness approximately 20% that of the interconnect metallization layer.