Methods of forming implant regions relative to transistor gates

A method of forming angled implants relative to a pair of adjacent transistor gates, comprising:

• forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
• etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and to partially form a pair of adjacent transistor gates from the gate stack;
• implanting at least one dopant at an angle other than 0° relative to vertical to form pocket implant regions under the partially formed adjacent transistor gates;
• and
• after the implanting, etching through the remaining portion of the electrically conductive material and completing formation of the pair of adjacent transistor gates.

A method of forming angled implants relative to a pair of adjacent transistor gates, comprising:

• forming a gate stack over a substrate, the gate stack comprising a first layer;
• etching only partially through the first layer to leave an unetched remaining portion of the first layer and to partially form a pair of adjacent transistor gates from the gate stack, the partially formed transistor gates have sidewall edges;
• forming a second layer along the sidewall edges of the partially formed pair of adjacent transistor gates;
• after forming the second layer, implanting at least one dopant at an angle other than 0° relative to vertical to form pocket implant regions under the partially formed adjacent transistor gates;
• and
• after the implanting, etching through the remaining portion of the first layer and completing formation of the pair of adjacent transistor gates.

A method of forming a DRAM assembly, comprising:

• forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
• etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and to partially form a pair of adjacent transistor gates from the gate stack;
• one of the adjacent transistor gates ultimately being incorporated into a first DRAM cell and the other of the adjacent transistor gates ultimately being incorporated into a second DRAM cell;
• forming pocket implant regions under the partially formed transistor gates;
• after the forming the pocket implant regions, etching through the remaining portion of the electrically conductive material, and completing formation of the pair of adjacent transistor gates;
• forming a heavily doped source/drain region shared by the adjacent transistor gates;
• forming first and second data storage devices for the first and second DRAM cells, respectively;
• and
• forming a bitline contact in electrical with the source/drain region.

A method of forming a pair of adjacent memory cells sharing a common bitline, comprising:

• forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
• etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and to partially form a pair of adjacent transistor gates from the gate stack;
• one of the adjacent transistor gates ultimately being incorporated into a first transistor and the other of the adjacent transistor gates ultimately being incorporated into a second transistor;
• defining three source/drain region locations relative to the partially formed transistor gates, a first of the source/drain region locations being associated with only the first transistor;
• a second of the source/drain region locations being shared by the first and second transistors, and a third of the source/drain region locations being associated with only the second transistor;
• forming a mask over the first and third source/drain region locations;
• while the mask is over the first and third source/drain region locations, implanting at least one dopant at an angle other than 0° relative to vertical to form pocket implant regions under the partially formed transistor gates;
• after the implanting, removing the mask, etching through the remaining portion of the electrically conductive material, and completing formation of the pair of adjacent transistor gates;
• forming first, second and third heavily doped source/drain regions at the first, second and third source/drain region locations, respectively;
• forming first and second data storage devices in electrical connection with the first and third source/drain regions, respectively;
• and
• forming a bitline contact in electrical with the second source/drain region.

A method of forming an electronic system, comprising:

• forming a gate stack over a substrate, the gate stack comprising a layer of electrically conductive material;
• etching only partially through the layer of electrically conductive material to leave an unetched remaining portion of the electrically conductive material and partially forming transistor gates from the gate stack;
• at least some of the partially formed transistor gates being paired adjacent transistor gates;
• forming pocket implant regions under at least some of the partially formed paired adjacent transistor gates;
• after the forming the pocket implants, etching through the remaining portion of the electrically conductive material, and completing formation of the transistor gates;
• forming source/drain regions proximate the transistor gates, some of the source/drain regions being shared by paired adjacent transistor gates;
• forming data storage devices in electrical connection with at least some of the source/drain regions;
• forming bitline contacts in electrical with at least some of the shared source/drain regions;
• the data storage devices, paired adjacent transistors and bitline contacts being incorporated into an array of memory cells;
• forming addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells;
• and
• forming a read circuit coupled to the array of memory cells for reading data from memory cells in the array of memory cells.