Vertical hard mask

A method of fabricating a microelectronic structure comprising the steps of:

• (a) forming a set of openings in a surface of a substrate, said openings having sidewalls that extend to a common bottom wall;
• (b) forming a film stack comprising a plurality of layers on each sidewall of said openings, said plurality of layers comprising at least a nitride diffusion barrier layer having a barrier thickness, a silicon layer deposited after said barrier layer and an oxide layer deposited after said silicon layer;
• (c) exposing said oxide layer on a lower portion of said structure and said silicon layer on an upper portion of said structure;
• (d) thermally nitriding simultaneously said silicon layer on said upper portion of said structure and said oxide layer on said lower portion of said structure, thereby forming a nitrided silicon layer having a first thickness limited by reaction kinetics and less than said barrier thickness on said silicon layer and a nitrided layer on said oxide layer having a thickness less than said first thickness;
• (e) etching in an oxide etch both said oxide layer in said lower portion and said nitrided silicon layer in said upper portion in an etch selective to nitride such that said oxide laver is removed while a portion of said nitrided silicon layer remains;
• (f) removing said silicon layer in said lower portion while said silicon layer is protected by a remaining portion of said nitrided silicon layer in said upper portion, and
• (g) simultaneously removing said diffusion barrier layer in said lower portion and said remaining portion of said nitrided silicon layer in said upper portion.