Deep submicron MOS transistor with increased threshold voltage
AssigneeNational Semiconductor Corporation
InventorsGobi R. Padmanabhan, Visvamohan Yegnashankaran, Reda Razouk
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Abstract
A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain regions. The side wall control gates can be used to substantially increase the threshold voltage of the transistor.
Claims20
A transistor formed in a semiconductor material of a first conductivity type, the transistor comprising:
- spaced-apart source and drain regions of a second conductivity type formed in the semiconductor material,
- the source region includes:
- a first lightly-doped region,
- a first heavily-doped region that is formed in the first lightly-doped region, and
- a second heavily-doped region that adjoins the first lightly-doped region and is spaced apart from the first heavily-doped region;
- and
- the drain region includes:
- a second lightly-doped region,
- a third heavily-doped region that is formed in the second lightly-doped region, and
- a fourth heavily-doped region that adjoins the second lightly-doped region and is spaced apart from the third heavily-doped region.
A method of using a MOS transistor formed in a semiconductor material of a first conductivity type,
- the transistor having:
- spaced-apart source and drain regions of a second conductivity type formed in the semiconductor material,
- the source region includes:
- a first lightly-doped region,
- a first heavily-doped region that is formed in the first lightly-doped region, and
- a second heavily-doped region that adjoins the first lightly-doped region and is spaced apart from the first heavily-doped region;
- and
- the drain region includes:
- a second lightly-doped region,
- a third heavily-doped region that is formed in the second lightly-doped region, and
- a fourth heavily-doped region that adjoins the second lightly-doped region and is spaced apart from the third heavily-doped region;
- a channel region located between the source and drain regions;
- a gate oxide layer formed over the channel region, and
- a channel gate formed on the gate oxide layer over the channel region, the channel gate having side walls;
- ground applied to the second heavily-doped region;
- a first positive voltage applied to the fourth heavily-doped region;
- and
- a second positive voltage applied to the channel gate, the second positive voltage being equal to or greater than a voltage required to invert the channel region of the MOS transistor;
- the transistor being biased off by:
- inducing a first potential in the first heavily-doped region that is substantially equal to ground, and
- inducing a second potential in the third heavily-doped region that is substantially equal to ground.
A method of forming a MOS transistor in a semiconductor material of a first conductivity type, the transistor having a layer of gate oxide formed over the semiconductor material, and a gate formed on the layer of gate oxide over a region of the semiconductor material, the method comprising the steps of:
- implanting the semiconductor material with a dopant of the second conductivity type to form a lightly-doped source region and a lightly-doped drain region;
- forming a side wall spacer that adjoins the side walls of the gate;
- and
- forming an outer gate on the layer of gate oxide to adjoin the side wall spacer over the lightly-doped source region and the lightly-doped drain region.
A transistor formed in a semiconductor material of a first conductivity type, the transistor comprising:
- spaced-apart diffusion regions of a second conductivity type formed in the semiconductor material,
- a diffusion region of the spaced-apart diffusion regions having:
- a first lightly-doped region,
- a first heavily-doped region that is formed in the first lightly-doped region, and
- a second heavily-doped region that adjoins the first lightly-doped region and is spaced apart from the first heavily-doped region;
- a channel region located between the source and drain regions;
- a gate oxide layer formed over the channel region;
- and
- a center gate formed on the gate oxide layer over the channel region, the center gate having side walls.
Dependencies are inferred from the claim text.