Multiport non-blocking high capacity ATM and packet switch
AssigneeTranSwitch Corporation
InventorsZheng Liu, Jiu An, Terry Xian, Ronald P. Novick
Life of this patent
Estimating the term…
Abstract
A multiport non-blocking high capacity ATM and packet switch is a single chip switching solution for ATM and packet systems. It is capable of 8×8 switching of 800 Mbit/s per port in both directions. The ports support UTOPIA Level 2 interfaces. The switch is non-blocking and lossless, incorporating a backpressure mechanism for eliminating congestion toward any one port. The switch supports prioritized and variable size cell and packet switching.
Claims16
A multiport non-blocking high capacity ATM and packet switch comprising:
- a) a single chip;
- b) an internal unidirectional time slotted looped bus located on said chip;
- c) a bus controller located on said chip and coupled to said bus;
- d) a microprocessor interface on said chip and coupled to said bus;
- and
- e) a plurality of switch ports on said chip and coupled to said bus, wherein each of said switch ports includes a UTOPIA interface wherein
- each port includes a full duplex interface.
A multiport non-blocking high capacity ATM and packet switch comprising:
- a) an internal bus;
- b) a bus controller coupled to said bus;
- c) a microprocessor interface coupled to said bus;
- d) a plurality of switch ports coupled to said bus, wherein each of said switch ports includes a UTOPIA interface and one of an ingress buffer and an egress queue;
- and
- e) congestion control means coupled to each of said one of an ingress buffer and an egress queue and to at least one of said UTOPIA interfaces such that said at least one of said UTOPIA interfaces is directed to stop accepting data when one of said one of an ingress buffer and an egress queue is congested, wherein
- each of said switch ports has an ingress buffer,
- said congestion control means is coupled to each of said ingress buffers and each of said UTOPIA interfaces such that a UTOPIA interface associated with a particular switch port is directed to stop accepting data when said ingress buffer associated with said particular switch port is congested.
A multiport non-blocking high capacity ATM and packet switch comprising:
- a) an internal bus;
- b) a bus controller coupled to said bus;
- c) a microprocessor interface coupled to said bus;
- d) a plurality of switch ports coupled to said bus, wherein each of said switch ports includes a UTOPIA interface and one of an ingress buffer and an egress queue:
- and
- e) congestion control means coupled to each of said one of an ingress buffer and an egress queue and to at least one of said UTOPIA interfaces such that said at least one of said UTOPIA interfaces is directed to stop accepting data when one of said one of an ingress buffer and an egress queue is congested, wherein
- each of said switch ports has an egress queue,
- said congestion control means is coupled to each of said egress queues and each of said UTOPIA interfaces such that a UTOPIA interface is directed to stop accepting data destined for an egress queue which is congested.
Dependencies are inferred from the claim text.