Memory refresh methods and circuits
AssigneeMosel Vitelic, Inc.
InventorsSteve S. Eaton, Michael Murray, Li-Chun Li
Life of this patent
Estimating the term…
Abstract
A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.
Claims26
A memory circuit comprising:
- a plurality of memory cells that need to be refreshed from time to time;
- circuitry for:
- receiving commands to perform memory access operations;
- for at least each command of a first type:
- performing a memory access operation specified by the command;
- at a predetermined time defined by the memory access operation, if a refresh is pending, then:
- (A) if the memory circuit has received an indication of a new command following the command of the first type, then not performing the refresh to leave the memory circuit available for executing the new command;
- (B) if the memory circuit has not received an indication of a new command following the command of the first type, then performing the refresh.
A method comprising:
- receiving commands to access a memory comprising a plurality of memory cells that need to be refreshed from time to time;
- for at least each command of a first type:
- performing a memory access operation specified by the command;
- at a predetermined time defined by the memory access operation, if a refresh is pending, then:
- (A) if the memory circuit has received an indication of a new command following the command of the first type, then not performing the refresh to leave the memory circuit available for executing the new command;
- (B) if the memory circuit has not received an indication of a new command following the command of the first type, then performing the refresh.
A method for operating a memory that comprises a plurality of memory cells that need to be refreshed from time to time, the method comprising issuing commands to access the memory, wherein at least each command C1 of a first type is issued in either:
- a long memory cycle, the long cycle being a cycle in which no indication of a new command is delivered to the memory for a while to allow the memory sufficient time to perform both a memory access operation specified by the command C1 and also to perform a refresh operation;
- or
- a short memory cycle, the short cycle being a cycle in which an indication of a new command is delivered to the memory early enough to block the memory from performing a refresh operation immediately after the command C1.
A system comprising:
- a memory comprising a plurality of memory cells that need to be refreshed from time to time;
- circuitry for issuing commands to access the memory, wherein at least each command C1 of a first type is issued so as to perform either:
- a long memory cycle, the long cycle being a cycle in which no indication of a new command is delivered to the memory for a while to allow the memory sufficient time to perform both a memory access operation specified by the command C1 and also to perform a refresh operation;
- or
- a short memory cycle, the short cycle being a cycle in which an indication of a new command is delivered to the memory early enough to block the memory from performing a refresh operation immediately after the command C1.
Dependencies are inferred from the claim text.