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US 6,721,216 B2Granted
Memory addressing structural test
AssigneeIntel Corporation
InventorsTak M. Mak, Michael R. Spica, Michael J. Tripp
Life of this patent
Estimating the term…
Abstract
An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.
Claims19
An apparatus, comprising:
- an address decoder;
- a plurality of word lines emanating from the address decoder;
- at least one memory cell connected to at least one of the word lines;
- and
- a signature analyzer connected to at least two of the plurality of word lines.
2 more elements
A method, comprising:
- setting the timing of a clock used to trigger the latching of inputs to a signature analyzer;
- transmitting an address to an address decoder connected to the inputs of the signature analyzer through a plurality of word lines;
- decoding the address using the address decoder;
- and
- triggering the signature analyzer with the clock to latch the state of the plurality of word lines connected to the inputs of the signature analyzer.
2 more elements
An apparatus, comprising:
- an address decoder;
- a signature analyzer;
- a plurality of circuits organized into a two-dimensional array comprising a first circuit, a second circuit, a third circuit and a fourth circuit;
- a first word line coupled to the address decoder, the signature analyzer, the first circuit and the second circuit;
- and
- a second word line coupled to the address decoder, the signature analyzer, the third circuit and the fourth circuit.
3 more elements
Dependencies are inferred from the claim text.