Electronic circuit and semiconductor storage device

An electronic circuit comprising:

• a first delay compensation circuit which receives a first power supply voltage, includes a transistor having a first characteristic, receives a first signal, and outputs a first output signal delayed by a first predetermined time;
• a second delay compensation circuit which receives a second power supply voltage, includes a transistor having a second characteristic, receives a second signal, and outputs a second output signal delayed by a second predetermined time;
• a first logic circuit which receives the first power supply voltage and the second output signal output from said second delay compensation circuit, performs first logic operation, and outputs a first operation result;
• and
• a second logic circuit which receives the first power supply voltage and the first output signal output from said first delay compensation circuit, performs second logic operation, and outputs a second operation result.

An electronic circuit comprising:

• a first level shifter which receives a first signal that has a second voltage at high level, boosts the second voltage to a first voltage, and outputs the first signal;
• a first delay compensation circuit which receives a first power supply voltage having the first voltage and the first signal output from said first level shifter and outputs a first output signal delayed by a first predetermined time;
• a second level shifter which receives the first output signal that has the first voltage at high level and output from said first delay compensation circuit, boosts the first voltage to the second voltage, and outputs the first output signal;
• a second delay compensation circuit which receives the second power supply voltage and the first signal that has the second voltage at high level and outputs a second output signal delayed by a second predetermined time;
• a third level shifter which receives the second output signal output from said second delay compensation circuit and boosts the second voltage of the second output signal of high level to the first voltage;
• a first logic circuit which receives the first power supply voltage and the second output signal output from said third level shifter, performs first logic operation, and outputs a first operation result;
• and
• a second logic circuit which receives the second power supply voltage having the second voltage and the first output signal output from said second level shifter, performs second logic operation, and outputs a second operation result.

A semiconductor storage device comprising:

• a memory cell array having a plurality of memory cells connected to a plurality of bit lines;
• column selection gates each provided for a corresponding one of the bit lines to select the bit line;
• a column decoder which generates a column selection signal for selectively driving said column selection gates;
• data buffers each of which is provided for a corresponding one of said column selection gates, receives data output from said corresponding column selection gate, and amplifies and outputs the data;
• a data buffer control logic circuit which generates a data buffer driving signal for selectively driving said data buffers;
• a first delay compensation circuit which receives a first power supply voltage and a timing signal and outputs a first output signal delayed by a first predetermined time to said data buffer control logic circuit;
• and
• a second delay compensation circuit which receives a second power supply voltage and the timing signal and outputs a second output signal delayed by a second predetermined time to said column decoder.

A semiconductor storage device comprising:

• a memory cell array having a plurality of memory cells connected to a plurality of bit lines;
• column selection gates each provided for a corresponding one of the bit lines to select the bit line;
• a column decoder which generates a column selection signal for selectively driving said column selection gates;
• data buffers each of which is provided for a corresponding one of said column selection gates, receives data output from said corresponding column selection gate, and amplifies and outputs the data;
• a data buffer control logic circuit which generates data buffer drive signals for selectively driving said data buffer;
• a first level shifter which receives a timing signal that has a second voltage at high level, and outputs the timing signal upon boosting the second voltage to a first voltage;
• a first delay compensation circuit which receives a first power supply voltage having the first voltage and the timing signal output from said level shifter and outputs a first output signal delayed by a first predetermined time;
• a second level shifter which receives the first output signal that has the first voltage at high level and output from said first delay compensation circuit, and outputs the first output signal to said data buffer control logic circuit upon boosting the first voltage to the second voltage;
• a second delay compensation circuit which receives the second power supply voltage and the timing signal that has the second voltage at high level, and outputs a second output signal delayed by a second predetermined time;
• and
• a third level shifter which receives the second output signal output from said second delay compensation circuit, boosts the second voltage of the second output signal of high level to the first voltage, and outputs the signal to said column decoder.

A semiconductor storage device comprising:

• a memory cell array having a plurality of memory cells connected to intersections of a plurality of word lines and a plurality of bit lines;
• a row decoder which generates a word line selection signal for selectively driving the word lines;
• sense amplifiers each of which is provided for a corresponding one of the bit lines, detects data output from the corresponding bit line, and output the data;
• a sense amplifier control circuit which generates a sense amplifier driving signal for selectively driving said sense amplifiers;
• a first level shifter which receives a timing signal that has a second voltage at high level, and outputs the timing signal upon boosting the second voltage to a first voltage;
• a first delay compensation circuit which receives a first power supply voltage having the first voltage and the timing signal output from said level shifter and outputs a first output signal delayed by a first predetermined time;
• a second level shifter which receives the first output signal that has the first voltage at high level and output from said first delay compensation circuit, and outputs the first output signal to said data buffer control logic circuit upon boosting the first voltage to the second voltage;
• a second delay compensation circuit which receives the second power supply voltage and the timing signal that has the second voltage at high level, and outputs a second output signal delayed by a second predetermined time;
• and
• a third level shifter which receives the second output signal output from said second delay compensation circuit, boosts the second voltage of the second output signal of high level to the first voltage, and outputs the signal to said column decoder.