Nonvolatile semiconductor memory device and methods for operating and producing the same
AssigneeSony Corporation
InventorsToshio Kobayashi, Hiroyuki Moriya, Ichiro Fujiwara
Life of this patent
Estimating the term…
Loading patent…
AssigneeSony Corporation
InventorsToshio Kobayashi, Hiroyuki Moriya, Ichiro Fujiwara
Estimating the term…
A nonvolatile semiconductor memory device with high reliability (free from troubles in storing data), a high charge injection efficiency, and enabling parallel operation in a VG cell array, includes channel forming regions, a charge storing film which consists of stacked dielectric films and is capable of storing a charge, two storage portions forming parts of the charge storing film and overlapping the channel forming regions, a single layer dielectric film between the storage portions and in contact with the channel forming region, a control gate electrode on the single layer dielectric film, and a memory gate electrode on the storage portions.
A nonvolatile semiconductor memory device comprising:
A method for operating a nonvolatile semiconductor memory device comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film,
A method for operating a nonvolatile semiconductor memory device comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film,
A method for operating a nonvolatile semiconductor memory device comprising memory cells arranged in a matrix to form a memory cell array, each of said memory cell comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film;
A method for operating a nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix to form a memory cell array, each of said memory cell comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film;
A method for operating a nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix to form a memory cell array, each of said memory cell comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film;
A method for operating a nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix to form a memory cell array, each of said memory cell comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film;
Dependencies are inferred from the claim text.