Bit encoded ternary content addressable memory cell

A ternary content addressable memory cell, comprising:

• a X memory cell;
• a Y memory cell;
• a compare circuit;
• and
• a common conductor pair coupled to the X memory cell, the Y memory cell and the compare circuit for receiving a first voltage value during a write operation and a second voltage value during a compare operation.

A ternary content addressable memory cell, comprising:

• a common conductor adapted to receive a first bit and a second bit, wherein the first bit is adapted to be written to and stored within the memory cell during a write operation or read from the memory cell during a read operation, and the second bit is adapted to be compared with the stored first bit during a compare operation of the memory cell;
• an X memory cell coupled to the common conductor for receiving the first bit, wherein the X memory cell consists of no more than six transistors, four of which form a main pair of cross-coupled inverters, and another two of which form main pass-through connections paths to respective ones of the main pair of cross-coupled inverters;
• a Y memory cell coupled to the common conductor, wherein the Y memory cell consists of no more than six transistors, four of which form a masking pair of cross-coupled inverters, and another two of which form masking pass-through connections paths to respective ones of the masking pair of cross-coupled inverters;
• a match line conductor adapted to receive a power supply voltage;
• a match line enable conductor adapted to receive the power supply voltage during times when the first bit is placed upon the common conductor and to receive a ground supply voltage during times when the second bit is placed upon the common conductor;
• and
• a compare circuit coupled to the common conductor for receiving the first bit and the second bit, wherein the compare circuit consists of no more than four transistors arranged in two pairs of transistors, wherein each pair of transistors is connected in series between the match line enable conductor and the match line conductor.

A method for operating a content addressable memory cell, comprising:

• (a) while forming a conductive path to a latch, strobing a bit line connected to the conductive path with a first voltage value placed upon the latch;
• (b) while maintaining the first voltage value upon the latch, strobing the bit line again with a second voltage value;
• and
• (c) if the first voltage value equals the second voltage value, forwarding a match signal from the memory cell.