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US 6,720,796 B1Granted
Multiple size memories in a programmable logic device
AssigneeAltera Corporation
InventorsSrinivas Reddy, David Jefferson, Christopher F. Lane, Vikram Santurkar, Richard Cliff
Life of this patent
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Abstract
A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
Claims16
A programmable logic device (PLD) comprising:
- an array of logic elements;
- a first memory block having a set of control logic and circuits,
- wherein the first memory block is disposed within the array of logic elements;
- and
- at least a second memory block having a set of control logic and circuits,
- wherein the second memory block is disposed within the array of logic elements, and
- wherein the first and second memory blocks have different memory sizes.
4 more elements
A programmable logic device (PLD) comprising:
- an array of logic elements;
- a first embedded memory block disposed within the array of logic elements;
- and
- at least a second embedded memory block disposed within the array of logic elements,
- wherein the first memory block has greater memory size than the second embedded memory block.
2 more elements
A method of designing a programmable logic device (PLD), comprising:
- designing the PLD such that the PLD includes an array of logic elements;
- designing the PLD to embed a first memory block within the array of logic elements;
- and
- designing the PLD to embed a second memory block within the array of logic elements,
- wherein the first and second memory blocks each have a set of control logic and circuits, and
- wherein the first and second memory blocks have different memory sizes.
3 more elements
Dependencies are inferred from the claim text.