Method for wafer test and wafer test system for implementing the method
AssigneeInternational Business Machines Corporation
InventorsDavid M. Audette, David L. Gardell, John F. Hagios
Life of this patent
Estimating the term…
Abstract
A method and system for testing wafers, and particularly a wafer test system employing probes to provide for electrical contact with a device under test (DUT) which is located on a wafer. More particularly, also provided is a method and system for implementing wafer tests where the probes first contact a simulated wafer which incorporates an array of spaced load cells to determine the optimum probe overdrive. The DUT is then tested at the optimum overdrive.
Claims17
A test system for testing devices under test (DUTs) located on a product wafer, said test system comprising:
- a support plate having a surface with a simulated wafer being arranged thereon, said simulated wafer including a load plate and a plurality of load cells retained in a spaced array interposed between said load plate and said support plate surface;
- a wafer probe arrangement including a device interface board mounting a plurality of probes being arrayed in opposed relationship to said load cells facing towards said load plate;
- and
- movable structure for imparting movement to said support plate for biasing said simulated wafer into contact with said plurality of probes to determine an optimum overdrive for a specific product which results in optimized probe force,
- said movable structure implementing said optimum overdrive during testing of said DUTs on said product wafer, whereby said probe force for each said probe of the plurality of probes responsive to pressure exerted between said respective load cells and probes is indicative of the plurality of the wafer surface at the final overdrive position for said support plate.
A method of testing devices under test (DUTs) located on a product wafer, said method comprising:
- providing a support plate with a surface with a simulated wafer being arranged thereon, said simulated wafer including a load plate and a plurality of load cells retained in a spaced array interposed between said load plate and said support plate surface;
- providing a wafer probe arrangement including a device interface board mounting a plurality of probes being arrayed in opposed relationship to said load cells facing towards said load plate;
- causing a movable structure to impart movement to said support plate for biasing said simulated wafer into contact with said at least probe, and determining the optimum overdrive for a specific product which results in optimized probe force;
- and
- implementing said optimum overdrive during testing of said DUTs on said product wafer, whereby said probe force for each said probe of the plurality of probes responsive to pressure exerted between said respective load cells and probes is indicative of the plurality of the wafer surface at the final overdrive position for said support plate.
Dependencies are inferred from the claim text.