PWM motor driving device

A PWM motor driving device comprising:

• a plurality of pairs of output transistors, each pair connected between two different voltages of a power source, and having an output stage for outputting voltage to each phase of a motor from a node between an upper output transistor connected to a higher-voltage side of the power source and a lower output transistor connected to a lower-voltage side of the power source and having;
• switching means for switching the upper and lower output transistors between ON and OFF according to a signal representing a rotational position of the motor;
• controlling means for controlling an amount of electric power supplied from the power source to the motor by controlling an ON/OFF duty factor of the upper output transistor according to a torque control signal;
• upper saturation preventing means for individually limiting voltages of a plurality of phases of the motor below a level above which the upper output transistor is saturated;
• lower phase detecting means for detecting, among the plurality of phases of the motor, the phase which is currently being driven by the lower output transistor;
• and
• lower saturation preventing means for limiting the voltage of the phase detected by the lower phase detecting means above a level below which the lower output transistor is saturated.

A PWM motor driving device comprising:

• a plurality of pairs of output transistors, each pair connected between two different voltages of a power source, and having an output stage for outputting voltage to each phase of a motor from a node between an upper output transistor connected to a higher-voltage side of the power source and a lower output transistor connected to a lower-voltage side of the power source and having;
• switching means for switching the upper and lower output transistors between ON and OFF according to a signal representing a rotational position of the motor;
• controlling means for controlling an amount of electric power supplied from the power source to the motor by controlling an ON/OFF duty factor of the lower output transistor according to a torque control signal;
• lower saturation preventing means for individually limiting voltages of a plurality of phases of the motor above a level below which the lower output transistor is saturated;
• upper phase detecting means for detecting, among the plurality of phases of the motor, the phase which is currently being driven by the upper output transistor;
• and
• upper saturation preventing means for limiting the voltage of the phase detected by the upper phase detecting means below a level above which the upper output transistor is saturated.

A PWM motor driving device comprising:

• a plurality of pairs of output transistors, each pair connected between two different voltages of a power source, and having an output-stage for outputting voltage to each phase of a motor from a node between an upper output transistor connected to a higher-voltage side of the power source and a lower output transistor connected to a lower-voltage side of the power source and having;
• switching means for switching the upper and lower output transistors between ON and OFF according to a signal representing a rotational position of the motor;
• controlling means for controlling an amount of electric power supplied from the power source to the motor by controlling an ON/OFF duty factor of the upper and lower output transistors according to a torque control signal;
• upper phase detecting means for detecting, among a plurality of phases of the motor, the phase which is currently being driven by the upper output transistor;
• upper saturation preventing means for limiting the voltage of the phase detected by the upper phase detecting means below a level above which the upper output transistor is saturated;
• lower phase detecting means for detecting, among the plurality of phases of the motor, the phase which is currently being driven by the lower output transistor;
• and
• lower saturation preventing means for limiting the voltage of the phase detected by the lower phase detecting means above a level below which the lower output transistor is saturated.