Semiconductor device, memory system and electronic apparatus
AssigneeSeiko Epson Corporation
InventorsJunichi Karasawa, Kunio Watanabe
Life of this patent
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Abstract
A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate—gate electrode layer, a second gate—gate electrode layer, a first drain—drain wiring layer, a second drain—drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The width of the first gate—gate electrode layer in the first load transistor is larger than the width of the first gate—gate electrode layer in the first driver transistor.
Claims15
A semiconductor device comprising:
- a first gate—gate electrode layer inducting a gate electrode of a first load transistor and a gate electrode of a first driver transistor;
- a second gate—gate electrode layer including a gate electrode of a second load transistor and a gate electrode of a second driver transistor;
- a first drain—drain wiring layer which forms a part of a connection layer that electrically connects a drain region of the first load transistor and a drain region of the first driver transistor;
- a second drain—drain wiring layer which forms a part of a connection layer that electrically connects a drain region of the second load transistor and a drain region of the second driver transistor;
- a first drain-gate wiring layer which forms a part of a connection layer that electrically connects the first gate—gate electrode layer and the second drain—drain wiring layer;
- and
- a second drain-gate wiring layer which forms a part of a connection layer that electrically connects the second gate—gate electrode layer and the first drain—drain wiring layer,
- wherein the first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers, respectively, and
- wherein a width of the first gate—gate electrode layer in the first load transistor is larger than the width of the first gate—gate electrode layer in the first driver transistor.
Dependencies are inferred from the claim text.