ESD protection device coupled between two high power lines
AssigneesWinbond Electronics Corp., Kabushiki Kaisha Toshiba
InventorWei-Fan Chen
Life of this patent
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Abstract
An ESD protection device coupled between two high power lines. The ESD protection device comprises a N-type well and a P-type well adjacent to each other, and a pair of PN MOS. The N-type well is coupled to a first high power line, and the P-type well is coupled to a low power line. The pair of PN MOS comprises a PMOS and a NMOS, formed respectively in the N-type well and P-type well. The PMOS and the NMOS is connected as an inverter powered by the first high power line and a second power line and to ensure that, in normal operation, either the PMOS or the NMOS is turned off.
Claims9
An electrostatic discharge (ESD) protection device coupled between a first high power line and a second high power line, comprising:
- a N-type well and a P-type well adjacent to each other, the N-type well being coupled to the first high power line and the P-type well being coupled to a low power line;
- and a pair of PN MOS comprising:
- a P-type metal-oxide-semiconductor transistor (PMOS) installed in the N-type well, comprising a first gate structure, a first P-type doped area and a second P-type doped area, the first gate structure being a gate of the PMOS and the first P-type doped area being coupled to the first high power line;
- and
- a N-type metal-oxide-semiconductor transistor (NMOS) installed in the P-type well, comprising a second gate structure, a first N-type doped area and a second N-type doped area, the second gate structure being a gate of the NMOS, wherein the gate of the NMOS is coupled to the gate of the PMOS so as to form an input end of the pair of PN MOS, the second P-type doped area is coupled to the second N-type doped area so as to from an output end of the pair of PN MOS, and the first N-type doped area is coupled to the second high power line;
- wherein in a normal operation, either the PMOS or the NMOS is turned off.
An electrostatic discharge protecting device coupled between a first high power line and a second high power line, comprising:
- a N-type well and a P-type well adjacent to each other, the N-type well being coupled to the first high power line and the P-type well being coupled to a low power line;
- and
- a plurality of pairs of PN MOS connected in series, each of the pairs of PN MOS comprising:
- a P-type metal-oxide-semiconductor transistor (PMOS) installed in the N-type well, comprising a first gate structure, a first P-type doped area and a second P-type doped area, the first gate structure being a gate of the PMOS and the first P-type doped area being coupled to the first high power line;
- and
- a N-type metal-oxide-semiconductor transistor (NMOS) installed in the P-type well, comprising a second gate structure, a first N-type doped area and a second N-type doped area, the second gate structure being a gate of the NMOS, wherein the gate of the NMOS is coupled to the gate of the PMOS so as to form an input end, the second P-type doped area is coupled to the second N-type doped area so as to form an output end, the first N-type doped area is coupled to the second high power line;
- wherein in normal operation, either the PMOS or the NMOS is turned off;
- wherein an input end of an first pair of PN MOS is coupled to the first high power line or the low power line.
Dependencies are inferred from the claim text.