Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices

A multiple-gate device structure, comprising:

• a substrate;
• a semiconductor depletion material with a first predetermined height and width overlying a predetermined portion of the substrate to form an active region;
• an isolation material formed on top of the substrate surrounding the active region so as to bury a bottom portion of the active region therein, thereby exposing a top portion of the active region;
• a gate dielectric layer covering the exposed portion of the top and two sidewalls of the top portion of the active region;
• and
• at least one gate electrode formed on top of the gate dielectric layer and extending through two sidewalls thereof to reach the isolation material,
• wherein source and drain regions of the multiple-gate device are separated by the gate electrode, wherein the exposed top portion of the active region has its top corners rounded.