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US 6,720,579 B2Granted
Semiconductor device and method of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYou-Cheol Shin, Kyu-Charn Park, Won-Hong Lee, Jung-Dal Choi
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Abstract
A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.
Claims11
A semiconductor device comprising:
- a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a semiconductor layer by a gate insulating layer, each gate line having an upper metal silicide layer;
- a plurality of source/drain regions formed on said semiconductor layer between said gate lines solely by carrying out impurity implantation processes.
A flash memory device comprising:
- an active region comprising a plurality of line shaped sub-regions, each being formed parallel to each other by means of an isolation layer on a substrate in a cell area;
- at least one common source line formed of wall shaped silicon material to be in contact with and cross said active region, having an upper metal silicide layer;
- a plurality of gate lines formed parallel to said common source line, arranged in order from both sides of said common source line to be symmetric with respect to said common source line and separated from said active region by said gate insulating layer, each having an upper metal silicide layer;
- a plurality of source/drain regions formed in said active region between said gate lines by carrying out impurity implantation;
- an interlayer insulating layer formed to cover said gate lines and said common source line;
- a plurality of bit lines formed parallel to said active region and connected with at least one of both sides of said gate lines positioned in both ends of said active region through contacts passing through said interlayer insulating layer;
- and
- at least a portion of said gate lines having a layered structure comprising a floating gate of a silicon layer, a separating dielectric layer, and a control gate having a silicon layer and a silicide layer, on each of junction regions on which said gate lines and said active regions cross each other.
5 more elements
Dependencies are inferred from the claim text.