US 6,720,249 B1 · Protective hardmask for producing interconnect structures

Abstract

The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide BLoK™, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric.

Claims29

Dependent claims

A method of protecting a dielectric layer on a semiconductor material during processing of the material, the method comprising:

providing a substrate of a semiconductor material and, optionally, an etch stop layer thereover;
depositing a bulk dielectric material over the semiconductor material;
depositing a first hardmask layer, comprising a material having a dielectric constant of about 2.5-8.0, over the bulk dielectric material;
depositing a sacrificial second hardmask layer disposed over the first hardmask layer;
subsequently processing the semiconductor material, the hardmask layers and the bulk dielectric material to make interconnect structures on the substrate, wherein during said processing the second hardmask layer entirely covers said first hardmask layer thereby protecting the first hardmask layer from processing exposure to substantially avoid both increase of said dielectric constant of the first hardmask layer and damage thereof;
removing the second hardmask layer after the interconnect structures are made, while permanently retaining the first hardmask layer over the bulk dielectric material;
and
further processing the semiconductor material, the first hardmask layer and the bulk dielectric material to form completed interconnect structures, wherein the first hardmask layer material protects the bulk dielectric material to substantially prevent alteration of the dielectric constant thereof during said steps of subsequent processing and further processing.

5 more elements

A method of forming interconnect structures comprising the steps of:

providing a semiconductor substrate;
depositing a bulk dielectric material over the semiconductor substrate;
depositing a first hardmask layer having a dielectric constant substantially equal to a dielectric constant of the bulk dielectric material;
depositing a second hardmask layer over the first hardmask layer;
depositing a third hardmask layer over the second hardmask layer;
etching one or more vias through the hardmask layers and the bulk dielectric material, wherein during said etching the second hardmask layer entirely covers said first hardmask layer thereby protecting the first hardmask layer from processing exposure to substantially avoid both increase of said dielectric constant of the first hardmask layer and damage thereof;
depositing a conductive material into the vias;
and
removing an excess of the conductive material by chemical mechanical planarization wherein the third and second hardmask layers are simultaneously removed, while
the first hardmask layer is retained over the bulk dielectric material to protect said bulk dielectric material and substantially prevent alteration of said dielectric constant thereof during said steps of etching said vias and removing said material and layers.

7 more elements

A method of forming an interconnect structure comprising:

providing a semiconductor substrate;
depositing a bulk dielectric material over the semiconductor substrate;
depositing a first, permanent hardmask layer having a dielectric constant substantially equal to a dielectric constant of the bulk dielectric material;
depositing at least a second hardmask layer over the first hardmask layer;
depositing and imaging at least a first photoresist layer over said structure;
processing said structure to form at least one via through the hardmask layers and the bulk dielectric material by transferring said at least first photoresist image and etching said hardmask layers and bulk dielectric material, wherein during said processing steps said at least second hardmask layer entirely covers said first hardmask layer thereby protecting the first hardmask layer from said processing exposure to substantially avoid both an increase of said dielectric constant of said first hardmask layer and damage thereof;
depositing a conductive material into the vias;
and
removing an excess of the conductive material by chemical mechanical planarization while simultaneously removing said at least second hardmask, whereby the first hardmask layer is retained over the bulk dielectric material to protect said bulk dielectric material and substantially prevent alteration of said dielectric constant thereof during said steps of etching said vias and removing said layers by chemical mechanical planarization.

6 more elements

A method of forming a dual damascene interconnect structure comprising:

providing a semiconductor substrate;
depositing a bulk dielectric material over the semiconductor substrate;
depositing a first hardmask layer having a dielectric constant substantially equal to a dielectric constant of the bulk dielectric material, said first hardmask layer comprising a permanent hardmask layer;
depositing a second hardmask layer over the first hardmask layer;
depositing a third hardmask layer over the second hardmask layer;
depositing and imaging a first photoresist layer over said third hardmask layer to expose portions thereof;
processing said structure by transferring said image into said exposed portions of said third hardmask layer for etching thereof to expose underlying portions of said second hardmask layer and subsequently removing any remaining photoresist layer, whereby said second hardmask layer protects said first hardmask layer from exposure to said processing steps to substantially avoid increase of said dielectric constant thereof;
depositing and imaging a second photoresist layer over said structure;
further processing said structure to form at least one via through the hardmask layers and the bulk dielectric material by transferring said second photoresist image into and etching said hardmask layers and bulk dielectric material wherein during said etching said second hardmask layer entirely covers said first hardmask layer thereby protecting the first hardmask layer from said further processing exposure thereby substantially avoiding both an increase of said dielectric constant of said first hardmask layer and damage thereof;
depositing a conductive material into the vias;
removing an excess of the conductive material by chemical mechanical planarization wherein the third and second hardmask layers are simultaneously removed, while the first hardmask layer is retained over the bulk dielectric material to protect said bulk dielectric material and substantially prevent alteration of said dielectric constant thereof during said steps of etching said vias and removing said material and layers by chemical mechanical planarization;
and
depositing a cap layer over said structure to completely cover said conductive material and said first hardmask layer, said first hardmask layer protecting said bulk dielectric material during depositing of said cap layer.

10 more elements

Dependencies are inferred from the claim text.

Protective hardmask for producing interconnect structures

Life of this patent

Protective hardmask for producing interconnect structures

Life of this patent

Abstract

Claims29