Method of forming shallow trench isolation in a semiconductor substrate
AssigneeSilicon Integrated System Corp.
InventorsTzu-Kun Ku, Chian-Kai Huang
Life of this patent
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Abstract
A method of forming shallow trench isolation in a semiconductor substrate. A hard mask having an opening is formed on the semiconductor substrate. The semiconductor substrate is etched through the opening to form a shallow trench. The semiconductor substrate is annealed in an ambient containing argon gas at a temperature of about 1150 to about 1200° C. for 1 to 2 hrs. An insulator is then formed on the hard mask to fill the shallow trench. The insulator is planarized while the hard mask is used as the polishing stop layer. Thereafter, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.
Claims16
A method of forming shallow trench isolation in a semiconductor substrate, comprising the steps in sequence of:
- forming a hard mask having a opening on the semiconductor substrate;
- etching the semiconductor substrate through the opening to form a shallow trench;
- annealing the semiconductor substrate in an ambient containing argon gas;
- forming a liner oxide on the surface of the shallow trench followed by deposition of a silicon oxide layer by high-density plasma chemical vapor deposition (HDPCVD) to form an insulator on the hard mask to fill the shallow trench;
- planarizing the insulator while the hard mask is used as the polishing stop layer;
- and
- removing the hard mask to expose the upper surface of the semiconductor substrate and leave a shallow trench insulation.
A method of forming shallow trench isolation in a semiconductor substrate, comprising the steps in sequence of:
- forming a hard mask having an opening on the semiconductor substrate;
- etching the semiconductor substrate through the opening to form a shallow trench;
- cleaning the semiconductor substrate with the shallow trench;
- annealing the semiconductor substrate in an ambient containing argon gas at a temperature of about 1150 to about 1200° C. for 1 to 2 hrs;
- forming a liner oxide on the surface of the shallow trench followed by deposition of a silicon oxide layer by high-density plasma chemical vapor deposition (HDPCVD) to form an insulator on the hard mask to fill the shallow trench;
- planarizing the insulator while the hard mask is used as the polishing stop layer;
- and
- removing the hard mask to expose the upper surface of the semiconductor substrate.
Dependencies are inferred from the claim text.