Memory manufacturing process using disposable ARC for wordline formation

A method of manufacturing an integrated circuit comprising:

• providing a silicon substrate having a charge-trapping layer over a core region and a gate oxide layer over a periphery region the silicon substrate having bitlines provided therein;
• depositing a polysilicon layer, a hard mask layer, a first anti-reflective coating layer, and a first photoresist layer over the silicon substrate;
• patterning the first photoresist layer, first anti-reflective coating layer, and hard mask layer over the core region and covering the periphery region;
• removing the first photoresist layer and the first anti-reflective coating layer;
• forming a polysilicon wordline from the polysilicon layer using the patterned hard mask layer in the core region;
• depositing a second anti-reflective coating layer and a second photoresist layer on the polysilicon wordline, the charge-trapping layer, and the hard mask layer in the periphery region wherein the second anti-reflective coating layer is of a disposable material;
• patterning the second photoresist layer, the second anti-reflective coating layer, and the hard mask layer over the periphery region and covering the core region;
• removing the second photoresist layer and the second anti-reflective coating layer from over the polysilicon wordline and the charge-trapping layer in the core region and the hard mask layer and the polysilicon layer in the periphery region;
• forming a polysilicon gate from the polysilicon layer using the patterned hard mask layer in the periphery region;
• removing the hard mask layer;
• and
• completing the integrated circuit.