US 6,714,885 B1 · Method for measuring number of yield loss chips and number of poor chips by type due to defect of semiconductor chips

Abstract

A method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips by which it is possible to remarkably improve the yield of semiconductor chips by measuring the number of yield loss chips due to defects of the chips, the maximum number of yield loss chips, and the number of the specific type of poor chips in an arbitrary process, an arbitrary equipment, and an arbitrary process section among semiconductor fabrication processes, thus managing the defects of the chips, is provided. The method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips includes the steps of checking defective chips among effective chips on a wafer which underwent a predetermined process using a defect examination equipment and plotting the checked defective chips on a first wafer map, forming disparity chips by pairing defective chips and non-defective chips adjacent to the defective chips on the first wafer map and determining a maximum reliability region formed of regions in which the disparity chips are located, plotting good chips and poor chips by type on a second wafer map using a yield measuring apparatus after completing the process, and classifying the number of good chips and poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map.

Claims8

Dependent claims

A method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips, comprising the steps of:

(a) checking defective chips among effective chips on a wafer which underwent a predetermined process using a defect examination equipment and plotting the checked defective chips on a first wafer map;
(b) forming disparity chips by pairing defective chips and non-defective chips adjacent to the defective chips on the first wafer map and determining a maximum reliability region formed of regions in which the disparity chips are located;
(c) plotting good chips and poor chips by type on a second wafer map using a yield measuring apparatus after completing the process;
and
(d) classifying the number of good chips and poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map, wherein, in the step (b), disparity chips are formed by sequentially searching defective chips on a wafer map and by combining the defective chip searched among non-defective chips which did not form a disparity chip with non-defective chips directly above, below, to the left and right and the defective chips which are not combined with the adjacent non-defective chips among the searched defective chips are excluded from the maximum reliability region.

2 more elements

A method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips, comprising the steps of:

(a) checking defective chips among effective chips on a wafer which underwent a predetermined process using a defect examination equipment and plotting the checked defective chips on a first wafer map;
(b) forming disparity chips by pairing defective chips and non-defective chips adjacent to the defective chips on the first wafer map and determining a maximum reliability region formed of regions in which the disparity chips are located;
(c) plotting good chips and poor chips by type on a second wafer map using a yield measuring apparatus after completing the process;
and
(d) classifying the number of good chips and poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map, wherein the step (d) comprises the steps of:
(d1) classifying the number of good chips and poor chips on a second wafer map, corresponding to defective chips and non-defective chips in the maximum reliability region on a first wafer map;
and
(d2) obtaining the generation ratio of poor chips and inferiority generation ratio by type to the defective chips and the generation ratio of the poor chips and the inferiority generation ratio by type to the non-defective chips based on the number of good chips and poor chips by type classified in the step (d1).

5 more elements

A method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips, comprising the steps of:

(a) checking defective chips among effective chips on a wafer which underwent a predetermined process using a defect examination equipment and plotting the checked defective chips on a first wafer map;
(b) forming disparity chips by pairing defective chips and non-defective chips adjacent to the defective chips on the first wafer map and determining a maximum reliability region formed of regions in which the disparity chips are located;
(c) plotting good chips and poor chips by type on a second wafer map using a yield measuring apparatus after completing the process;
(d) classifying the number of good chips and poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map;
and
(e) obtaining the generation ratio of poor chips and inferiority generation ratio by type to the defective chips and the generation ratio of the poor chips and the inferiority generation ratio by type to the non-defective chips based on the number of good chips and poor chips by type classified in the step (d).

3 more elements

Dependencies are inferred from the claim text.

Method for measuring number of yield loss chips and number of poor chips by type due to defect of semiconductor chips

Life of this patent

Method for measuring number of yield loss chips and number of poor chips by type due to defect of semiconductor chips

Life of this patent

Abstract

Claims8