US 6,714,454 B2 · Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell

Abstract

A four-terminal dual-bit double polysilicon source-side injection flash EEPROM cell, capable of storing two bits of information includes a right junction (which can serve as a cell drain or a source), a left junction (which can serve as a cell source or drain), a select-gate, and two floating gates. The two floating gates are insulated from the select-gate by an inter gate dielectric. The inter-gate dielectric has a “weak region” so that during erase mode electrons can tunnel from the floating gate to the select-gate. The two bits in the cell are to be separately read or programmed, but are to be erased simultaneously. Programming of each bit is achieved through hot-carrier injection, while simultaneous erase of the two bits is achieved through electron tunneling.

Claims16

Dependent claims

A method of operating a memory cell having first and second junctions in a body region, the first and second junctions being separated by a channel region, the separation between the first and second junctions defining a cell channel length extending horizontally, each of the first and second junctions having a vertically-extending width, a horizontally-extending length, and a depth, the memory cell further having first and second floating gates extending over the channel region, and a select-gate extending over the first and second floating gates and extending across the entire length of each of the first and second junctions, the select gate being separated from the first and second floating gates only by an insulating layer, the method comprising:

storing a first bit of data in the first floating gate;
storing a second bit of data in the second floating gate;
in a first read operation, reading only the first bit of data;
and
in a second read operation, reading only the second bit of data.

2 more elements

A method of programming a memory cell having a source region and a drain region in a body region, the source and drain regions being separated by a channel region, the separation between the source and drain regions defining a cell channel length extending horizontally, each of the source and drain regions having a vertically-extending width, a horizontally-extending length, and a depth, the memory cell further having a first floating gate extending over a first portion of the channel region and overlapping the drain region, a second floating gate extending over a second portion of the channel region and overlapping the source region, and a select-gate extending over the first and second floating gates and extending across the entire length of each of the source and drain regions, the select gate being separated from the first and second floating gates only by an insulating layer, the method comprising:

changing an electrical potential of the first floating gate by applying a first set of voltages to the select gate, the body region, the drain region, and the source region to induce injection of hot electrons into the first floating gate from the channel region under the source-side of the first floating gate;
and
changing the electrical potential of the second floating gate by applying a second set of voltages to the select gate, the body region, the drain region, and the source region to induce injection of hot electrons into the second floating gate from the channel region under the drain-side of the second floating gate.

Dependencies are inferred from the claim text.

Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell

Life of this patent

Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell

Life of this patent

Abstract

Claims16