Silicon-based inductor with varying metal-to-metal conductor spacing

#The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a novel on-chip inductor with varying spacing between the turns of the inductor to optimize inductor performance by reducing substrate as well as conductor eddy current.

#Increasing demands for personal mobile communication equipment have motivated recent research activities to focus on the development of inexpensive, small size, low power consumption, and low noise level systems. Advances in technology are making it possible to develop radio frequency (RF) circuits on a single silicon chip. Silicon, with its mature technology, low fabrication cost as well as high packing density is recognized as the only material able to satisfy the needs of a rapidly growing communication market. To fulfill all the above-mentioned requirements, one of the most important and indispensable circuit components is the on-chip silicon-based spiral inductor.

#Nevertheless, difficulties of realizing high quality factor (Q) inductors pose a great challenge for silicon radio frequency integrated circuit (IC) applications. One difficulty in achieving such high-Q inductors is dealing with substrate losses. Several fabricating techniques, methods and processes have been proposed to improve the performance of silicon-based on-chip inductors because of their high substrate losses compared to the lossless substrate used in monolithic microwave integrated circuit (MMIC) technology (see e.g., U.S. Pat. No. 5,884,990 to Joachim N. Burghartz et al., entitled “Integrated Circuit Inductor”, issued Mar. 23, 1999; N. Camilleri, D. Lovelace, J. Costa and N. David, “New Development Trends for Silicon RF Device Technologies”, IEEE Electron Device Letters, Vol. 17, No. 9, pp. 428-430, September 1996; John R. Long and Miles A. Copeland, “The Modeling, Characterization and Design of Monolithic Inductors for Silicon RF ICs”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 3, pp. 357-368, March 1997; and Joachim N. Burghartz, A. E. Ruehli, M Soyuer, D. Nguyen Ngoc, and Keith A. Jenkins, “Novel Substrate Contact Structure for High-Q Silicon Integrated Spiral Inductors,” Tech. Dig. Int. Electron Devices Meeting (IEDM), pp. 55-58, 1997).

#The accompanying drawings, which are incorporated in and form a part of this specification, illustrates embodiments of the invention and, together with the description, serve to explain the principles of the invention:

#FIG. 1A is a top sectional view illustrating a conventional silicon based inductor.

#FIG. 1B is a side sectional view the conventional silicon-based inductor of FIG. 1A, illustrating substrate magnetic loss mechanisms.

#The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted.

#Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

#Embodiments of the present invention provide for an improved spiral inductor by optimizing its spiral's metal-to-metal conductor spacing. Thus, through such layout optimization techniques, the performance of a conventional silicon-based spiral inductor can be enhanced without any process modifications. In one embodiment, the spacing between adjacent turns is narrower near the outside of the inductor spiral. Both substrate eddy currents and spiral conductor eddy currents are reduced, in embodiments of the present invention.