Back to results
US 6,714,061 B2Granted
Semiconductor controlled rectifier / semiconductor controlled switch based ESD power supply clamp with active bias timer circuitry
AssigneeIntel Corporation
InventorScott Hareland
Life of this patent
Estimating the term…
Abstract
A circuit for reducing leakage current in an ESD overvoltage protection circuit is described. Specifically, the circuit uses a semiconductor controlled rectifier or a semiconductor controlled switch to minimize the leakage.
Claims3
A method to reduce leakage in an electrostatic discharge (ESD) protection circuit, comprising:
- placing a semiconductor controlled switch (SCS) in a forward blocking state during steady state operation, wherein the SCS comprises a first terminal coupled to a voltage source, a second terminal coupled to ground, a third terminal coupled to a first inverter, and a fourth terminal coupled to a second inverter;
- and
- triggering the SCS into a forward conducting state during an ESD event, wherein the first inverter sends a first signal to the third terminal and the second inverter sends a second signal to the fourth terminal.
Dependencies are inferred from the claim text.