Polishing of conductive layers in fabrication of integrated circuits

A wafer comprising:

• a semiconductor substrate;
• a dielectric formed over the semiconductor substrate, the dielectric having a plurality of trenches therein;
• conductive lines in the trenches;
• wherein the dielectric and the conductive material in the trenches form a first structure and a second structure spaced from the first structure, wherein each of the first and second structures have the same distance between corresponding points of adjacent trenches, wherein the first structure is adjoined on at least two opposite sides by first regions which do not have said conductive material or in which said conductive material has a lower density than in the first structure, and the second structure is adjoined on at least two opposite sides by second regions which do not have said conductive material or in which said conductive material has a lower density than in the second structure, wherein the second regions are disjoint from the first regions or overlap the first regions;
• wherein the second structure is smaller in size than the first structure, the first structure is part of a functional circuitry, and the second structure is a test structure not forming part of any functional circuitry manufactured in the wafer;
• wherein the first structure is at least as large as a square of 1×1 mm, and the second structure is no larger than a square of 60×60 μm.

A wafer comprising:

• a semiconductor substrate;
• a dielectric formed over the semiconductor substrate, the dielectric having a plurality of trenches therein;
• conductive lines in the trenches;
• wherein the dielectric and the conductive material in the trenches form a first structure and a second structure spaced from the first structure, wherein each of the first and second structures have the same distance between corresponding points of adjacent trenches, wherein the first structure is adjoined on at least two opposite sides by first regions which do not have said conductive material or in which said conductive material has a lower density than in the first structure, and the second structure is adjoined on at least two opposite sides by second regions which do not have said conductive material or in which said conductive material has a lower density than in the second structure, wherein the second regions arc disjoint from the first regions or overlap the first regions;
• wherein the second structure is smaller in size than the first structure,
• wherein the second structure overlaps a scribe line or a margin area of the wafer;
• and
• wherein at the location of the second structure the wafer does not have any layers not present in the first structure.