Method for fabricating a split gate flash memory cell

A method for fabricating a split gate flash memory cell, comprising the steps of:

• providing a substrate having a doped region and a first conductive layer formed over the doped region;
• forming a floating gate and a first insulating layer successively over the substrate on both sides of the first conductive layer, wherein the floating gate is insulated from the first conductive layer and the substrate;
• forming a conformable second insulating layer, a conformable second conductive layer, and a third conductive layer on the substrate and the first insulating layer successively;
• forming a third insulating layer on the third conductive layer;
• etching back the third insulating layer to expose the third conductive layer;
• etching back the exposed third conductive layer and the second conductive layer successively to expose the second insulating layer;
• forming a cap layer on the exposed third and second conductive layers;
• removing the third insulating layer to form an opening and expose the third conductive layer;
• and
• removing the third and second conductive layers under the opening to expose the second insulating layer and form a control gate composed of the remaining third and second conductive layers underlying the cap layer.