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AssigneeSTMicroelectronics S.r.l.
InventorsPaolo Giuseppe Cappelletti, Alfonso Maurelli
Estimating the term…
A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrodes for the second transistors; in the first portions of the semiconductor substrate, forming source and drain regions for the first transistors; in the second portions of the semiconductor substrate, forming source and drain regions for the memory cells; in the third portions of the semiconductor substrate, forming source and drain regions for the second transistors.
An integrated circuit integrated in a same semiconductor chip, comprising low operating voltage high-performance logic circuitry, a memory device operating at a high operating voltage higher than said low operating voltage, and high operating voltage circuitry operating at said high operating voltage, wherein the high operating voltage circuitry comprises a first transistor having a first gate oxide layer with a first thickness, the memory device comprises floating-gate memory cells having a second gate oxide layer with a second thickness, the low operating voltage circuitry comprises second transistors having a third gate oxide layer with a third thickness, and the first transistor has a gate electrode formed from a same polysilicon layer as the one from which a floating-gate electrode of the memory cells is also formed, and the second transistors have a gate electrode formed from a same polysilicon layer as the one from which a control-gate electrode of the memory cells is also formed, wherein the first transistor further includes a dielectric layer that surrounds the gate electrode of the first transistor and contacts a top side and two lateral sides of the gate electrode of the first transistor.
A circuit formed in a semiconductor substrate, comprising:
Dependencies are inferred from the claim text.