Method for fabricating source/drain devices

A method for fabricating source/drain devices, comprising:

• providing a silicon substrate having a gate, a first doped area on a first side of the gate on the silicon substrate, and a second doped area on a second side of the gate on the silicon substrate with spaces between;
• forming a patterned photo resist layer on the semiconductor substrate having a opening on the second side of the gate, wherein the width of the exposed gate is 2 μm;
• and
• implanting and annealing the silicon substrate to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.

A method for fabricating source/drain devices, comprising:

• providing a semiconductor substrate having a pad layer, a gate, a first isolating area on a first side of the gate, and a second isolating area on a second side of the gate, wherein the gate has a spacer on the sidewall of the gate;
• forming a first patterned photo resist layer as a mask to implant ions into the semiconductor substrate to form a first doped area and a second doped area, wherein the first doped area is positioned between the gate and the first isolating area, and the second doped area is positioned between the gate and second isolating area;
• forming a second patterned photo resist layer on the semiconductor substrate having an opening on the second side between the gate and the second isolating area, wherein the exposed gate is less than half the width of the gate;
• implanting and annealing the semiconductor substrate using the patterned photo resist layer as a mask to form a dual diffusion area on the second side of the gate;
• and
• removing the second patterned photo resist layer.

A method for fabricating source/drain devices, comprising:

• providing a silicon substrate having a pad oxide layer, a gate, a first isolating area on a first side of the gate, and a second isolating area on a second side of the gate, wherein the gate has a spacer on the sidewall of the gate;
• forming a first patterned photo resist layer as a mask to implant the silicon substrate to form a first doped area and a second doped area, wherein the first doped area is positioned between the gate and the first isolating area, and the second doped area is positioned between the gate and second isolating area;
• removing the first patterned photo resist layer;
• forming a second patterned photo resist layer on the silicon substrate having a opening on the second side between the gate and the second isolating area, wherein the width of the exposed gate is 2 μm;
• implanting and annealing the silicon substrate using the patterned photo resist layer as a mask to form a dual diffusion area on the second side of the gate;
• and
• removing the second patterned photo resist layer.