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US 6,713,334 B2Granted
Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Youngmin Kim, Amitava Chatterjee
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Abstract
An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.
Claims2
A method of fabricating low and high voltage CMOS transistors comprising the steps of:
- masking all core NMOS and I/O NMOS transistors;
- implanting both core PMOS and I/O PMOS transistors;
- removing mask from core NMOS transistors I/O NMOS transistors and masking core PMOS transistors and I/O PMOS transistors;
- implanting both core and I/O NMOS transistors;
- and
- masking all I/O NMOS transistors and I/O PMOS transistors and simultaneously implant phosphorus in both NMOS and PMOS core transistors.
3 more elements
Dependencies are inferred from the claim text.