Ferroelectric memory device using via etch-stop layer and method for manufacturing the same

A method for manufacturing a ferroelectric memory device, the method comprising:

• forming a lower interlayer insulating layer on a semiconductor substrate;
• forming at least two adjacent ferroelectric capacitors on the lower interlayer insulating layer;
• forming an interlayer insulation layer disposed between the ferroelectric capacitors and extending to substantially the same height as the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed;
• forming a via etch-stop layer on the semiconductor substrate including the interlayer insulation layer;
• forming a first upper interlayer insulating layer overlying the via etch-stop layer;
• forming strapping lines over the first upper interlayer insulating layer;
• forming a second upper interlayer insulating layer covering the strapping lines;
• forming a slit-shaped common via hole by selectively etching the second and first upper interlayer insulating layers between the at least two adjacent ferroelectric capacitors using the via etch-stop layer as an etch end point;
• exposing the top surface of the ferroelectric capacitors by etching the via etch-stop layer within the slit-shaped common via hole;
• and
• forming a plate line by depositing a conductive layer within the slit-shaped common via hole to commonly contact the at least two adjacent ferroelectric capacitors and to contact the interlayer insulation layer between the at least two ferroelectric capacitors.