Logic architecture for single event upset immunity

A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a circuit layout that defines a circuit comprising:

• a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;
• a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit;
• and
• a conversion circuit having an output, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,
• wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

A computer readable medium storing a data structure corresponding to a standard cell, the standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a circuit schematic that defines a circuit comprising:

• a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;
• a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit;
• and
• a conversion circuit having an output, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,
• wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

A computer readable medium storing a data structure corresponding to a standard cell, the standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a circuit layout that defines a circuit comprising:

• a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;
• a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit;
• and
• a conversion circuit having an ouput, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,
• wherein the first and second versions of the first input signals correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a schematic that defines a circuit comprising:

• a first inverter circuit having an ouput, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;
• a second inverter having an ouput, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal;
• a third inverter circuit having an output, a first input coupled to receive a first version of a signal output by the first inverter circuit, and a second input coupled to receive a second version of a signal output by the second inverter circuit;
• a fourth inverter circuit having an output, a first input coupled to receive a second version of a signal output by the first inverter circuit, and a second input coupled to receive a first version of a signal output by the second inverter circuit;
• and
• a conversion circuit having an output, a first input coupled to the output of the third inverter circuit, and a second input coupled to the output of the fourth inverter circuit, the conversion circuit comprising a fifth inverter circuit that forms a portion of a current path within a sixth inverter circuit,
• wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse, the first and second versions of the signal output by the first inverter circuit correspond to an identical value in the absence of a transient pulse, and the first and second versions of the signal output by the second inverter circuit correspond to an identical value in the absence of a transient pulse.

A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a schematic that defines a circuit comprising:

• a first NAND circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;
• and
• a second NAND circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second NAND circuit logically equivalent to the first NAND circuit,
• wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

A data structure corresponding to a standard cell associated with a standard cell library, the data structure comprising a data field corresponding to a schematic that defines a circuit comprising:

• a first NOR circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;
• and
• a second NOR circuit having an output a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second NOR circuit logically equivalent to the first NOR circuit,
• wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

A method, comprising:

• generating first and second intermediate signals each having a first logic value in response to first and second input signals each having a second logic value;
• maintaining at least one of the first and second intermediate signals at the first logic value in response to a transient pulse superimposed on one of the first and second input signals;
• generating an output signal having the second logic value in response to the first and second intermediate signals each having the first logic value;
• and
• maintaining the output signal at second logic value in response to a transient pulse superimposed on one of the first and second intermediate signals.

A method, comprising:

• generating a first output signal having a logic value that is equal to a logical inversion of first and second versions of an input signal;
• generating a second output signal having the logic value;
• and
• maintaining at least one of the first and second output signals at the logic value in response to a transient pulse superimposed on one of the versions of the input signal.

A method, comprising:

• generating a first output signal having a logic value that is equal to a logical NAND of first and second versions of a first input signal and first and second versions of a second input signal;
• generating a second output signal having the logic value;
• and
• maintaining at least one of the first and second output signals at the logic value in response to a transient pulse superimposed on one of the versions of the first and second input signals.

A method, comprising:

• generating a first output signal having a logic value that is equal to a logical NOR of first and second versions of a first input signal and first and second versions of a second input signal;
• generating a second output signal having the logic value;
• and
• maintaining at least one of the first and second output signals at the logic value in response to a transient pulse superimposed on one of the versions of the first and second input signals.