Back to results
US 6,693,333 B1Granted
Semiconductor-on-insulator circuit with multiple work functions
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
Estimating the term…
Abstract
An integrated circuit can include gate structures designed to effect a work function of a transistor. A first set of gate structures can have a first work function and a second set of gate structures can have a second work function. The gate structures include metal layers to affect changes in the work function. The work function can affect the threshold voltage associated with the transistors. The transistor can be built on a silicon-on-insulator substrate.
Claims19
An integrated circuit comprising:
- a plurality of gate structures, the gate structures are each disposed between a source region and a drain region and include a polysilicon layer, wherein a first gate structure of the gate structures includes a first ultra-thin metal layer and a second gate structure of the gate structures does not include the first ultra-thin metal layer, wherein the first gate structure and the second gate structure include a second ultra-thin metal layer, wherein the first and second ultra-thin metal layers include a metal material, the metal material being a non-compound metal material, whereby the second ultra-thin metal layer affects the work function of the first gate structure and the second gate structure, whereby the first ultra-thin metal layer affects a work function associated with the first gate structure, wherein the first ultra-thin metal layer and the second ultra-thin metal are less than 30 Å thick, wherein the gate structures include a third gate a structure, the third gate structure not including the first ultra-thin metal layer or the second ultra-thin metal layer, whereby the third gate structure has a work function different than the first gate structure and the second gate structure.
An integrated circuit comprising:
- a plurality of gate structures, the gate structures are each disposed between a source region and a drain region, wherein a first gate structure of the gate structures includes a first ultra-thin metal layer and a second gate structure of the gate structures does not include the first ultra-thin metal layer, wherein the first gate structure and the second gate structure include a second ultra-thin metal layer, whereby the second ultra-thin metal layer affects the work function of the first gate structure and the second gate structure whereby the first ultra-thin metal layer affects a work function associated with the first gate structure, wherein the gate structures include a third gate structure, the third gate structure not including the first ultra-thin metal layer or the second ultra-thin metal layer, whereby the third gate structure has a work function different than the first gate structure and the second gate structure.
An integrated circuit comprising:
- a plurality of gate structures, the gate structures are each disposed between a source region and a drain region, wherein a first gate structure of the gate structures includes a first ultra-thin metal layer and a second gate structure of the gate structures does not include the fist ultra-thin metal layer, whereby the first ultra-thin metal layer affects a work function associated with the fist gate structure, wherein the first gate structure and the second gate structure further include polysilicon, wherein the polysilicon is more than 1000 Å thick, wherein the first ultra-thin metal layer is disposed below the polysilicon of the first gate structure and the first and second gate structures include a second ultra-thin layer and the second ultra-thin metal layer is disposed below the polysilicon of the second gate structure.
An integrated circuit comprising:
- a plurality of layered gate conductors including a polysilicon layer and a first thin metal layer, wherein a first gate conductor of the gate conductors includes a second thin metal layer and a second gate conductor of the gate conductors does not include the second thin metal layer wherein the first thin metal layer is disposed below the polysilicon layer.
Dependencies are inferred from the claim text.