Varactor having improved Q-factor and method of fabricating the same using SiGe heterojunction bipolar transistor

#1. Field of the Invention

#The present invention relates to a varactor having variable capacitance and a method of fabricating the same, and more particularly, to a varactor having an improved Q-factor and a method of fabricating the same using a silicon-germanium (SiGe) heterojunction bipolar transistor.

#2. Description of the Related Art

#The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

#FIG. 1 is a sectional view of a typical silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), particularly, a typical self-alignment type SiGe HBT;

#FIG. 2 is a sectional view of a varactor using the self-alignment type SiGe HBT of FIG. 1;

#Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention is not restricted to the following embodiments, and many variations are possible within the spirit and scope of the present invention.

#FIG. 3 is a sectional view of a varactor according to a first embodiment of the present invention. Referring to FIG. 3, an n+-type buried collector region 301 is formed in the upper surface portion of a p-type semiconductor substrate 300. An n-type collector region 302 and an n+-type collector contact region 303 are formed on the n+-type buried collector region 301 such that they are separated by an isolation layer 304. A p+-type external base region 315 is formed on the n-type collector region 302. A p+-type silicon-germanium (SiGe) base region 305 is formed on the p+-type external base region 315. A metal silicide layer 312 is formed on the p+-type SiGe base region 305. A first metal layer 309 used as an anode electrode is formed on a partial surface of the metal silicide layer 312 such that it is electrically connected to the p+-type SiGe base region 305 through the metal silicide layer 312.

#An n+-type polysilicon layer 307 used as a collector conductive layer is formed on the n+-type collector contact region 303. The metal silicide layer 312 is also formed on the n+-type polysilicon layer 307. A second metal layer 311 used as a cathode electrode is formed on a partial surface of the metal silicide layer 312 such that it is electrically connected to the n-type collector region 302 through the metal silicide layer 312, the n+-type collector conductive layer 307, the n+-type collector contact region 303, and the n+-type buried collector region 301. The first metal layer 309 and the metal silicide layer 312 contacting the first metal layer 309 are electrically insulated from the second metal layer 311 and the metal silicide layer 312 contacting the second metal layer 311 by an insulation layer 313. Reference numeral 314 denotes an impurity region for isolating devices.