Four transistors static-random-access-memory

A four transistors static-random-access-memory cell, comprising:

• a first P-type transistor, said first P-type transistor comprising a first P-type enlarged source, a first P-type enlarged drain and a first gate, wherein the length of the channel under said first gate and between said first P-type enlarged source and said first P-type enlarged drain is smaller than width of said first gate;
• a second P-type transistor, said second P-type transistor comprising a second P-type enlarged source, a second P-type enlarged drain and a second gate, wherein the length of the channel under said second gate and between said second P-type enlarged source and said second P-type enlarged drain is smaller than width of said second gate;
• a first N-type transistor, said first N-type transistor comprising a first N-type drain, a first N-type source, a third gate and a first P-type extra source, wherein said first P-type extra source is located along with said first N-type source and faced to said first N-type drain, the length of the channel under said third gate and between said first N-type source and said first N-type drain being smaller than the width of said third gate;
• and
• a second N-type transistor, said second N-type transistor comprising a second n-type drain, a second N-type source, a fourth gate and a second P-type extra source, wherein said second P-type extra source is located along with said second N-type source and faced to said first N-type drain, the length of the channel under said fourth gate and between said second N-type source and said second N-type drain being smaller than the width of said fourth gate.