Semiconductor memory device and manufacturing method thereof
AssigneesMatsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies, Inc.
InventorsFumihiko Noro, Seiki Ogura
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Abstract
A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.
Claims8
A semiconductor memory device, comprising:
- a stepped region between a first main surface of a semiconductor substrate and a second main surface of the semiconductor substrate, the second main surface is positioned lower than the first main surface;
- a control gate electrode disposed on the first main surface via a first insulating film;
- a floating gate electrode disposed over the stepped region via a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode via a third insulating film;
- wherein the stepped region comprises a plurality of stepped portions.
A semiconductor memory device, comprising:
- a stepped region between a first main surface of a semiconductor substrate and a second main surface of the semiconductor substrate, the second main surface is positioned lower than the first main surface;
- a control gate electrode disposed on the first main surface via a first insulating film;
- a floating gate electrode disposed over the stepped region via a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode via a third insulating film;
- wherein the stepped region comprises a first stepped portion and a second stepped portion,
- wherein the first stepped portion is disposed between the first main surface and the second stepped portion, and
- wherein the second stepped portion is disposed between the first stepped portion and the second main surface.
Dependencies are inferred from the claim text.