Semiconductor memory having a plurality of memory-cell arrays

#The invention relates to a semiconductor memory having a plurality of memory-cell arrays, a plurality of sense-amplifier areas and a plurality of driver areas on a semiconductor substrate of a first conductivity type, each of the multiple sense-amplifier areas and multiple driver areas containing at least one first well of the first conductivity type and/or at least one second well of a second conductivity type, and each first well of the driver areas being isolated from the semiconductor substrate by a buried horizontal layer of the second conductivity type.

#In traditional semiconductor memories having a matrix-like layout of the memory-cell arrays, a driver area (segment driver) and a sense-amplifier area are arranged near each memory-cell array. In order to be able to drive each of the cells independently of the potential of the actual substrate of the semiconductor memory, the cells and their select transistors are isolated from the substrate. This is done by arranging each cell array and each area respectively in its own well. Each well occupies space on the surface of the semiconductor memory, however, so that the total area required for the memory increases.

#The object of this invention is to create a semiconductor memory that requires less space.

#FIG. 1 shows schematically a semiconductor memory according to the state of the art having a matrix-type arrangement of memory-cell arrays.

#FIGS. 2A and 2B show a cross-section through a driver cell and a sense amplifier respectively according to the state of the art.

#FIGS. 3A and 3B show a cross-section through a driver cell according to the invention and through a sense amplifier according to the invention respectively.

#FIG. 1 shows the matrix-type arrangement of the cell arrays of a semiconductor memory 1. Areas containing densely packed independent memory cells (memory-cell arrays) are labeled 2, the sense-amplifier areas are labeled 3, and the driver areas for the memory-cell arrays 2 are labeled 4. Word lines 5 and bit lines 6, which can be used to read the contents of each individual memory cell 2 or to write to each individual memory cell 2 are taken out laterally from the semiconductor memory 1.

#FIGS. 2A and 2B show in cross-section the detailed structure of a driver cell 4 and a sense-amplifier 3 respectively according to the state of the art.

#The driver cell 4 according to the state of the art shown in FIG. 2A is fabricated on a substrate 7 and arranged between two memory-cell arrays, parts of which are shown on the left and right edge of FIG. 2A. In the illustrated embodiment the substrate 7 is of type p. The memory-cell arrays contain, on a horizontal buried layer 8 that isolates the memory cell 2 from the underlying substrate 7, a first well of the first conductivity type, so in this case of type p. The driver cell 4 between the memory-cell arrays 2 normally contains a plurality of p- and n-doped wells, of which a first well 9 of type p and a second well 10 of type n are shown. The first well 9 is therefore of the same conductivity type as the substrate 7. In order to electrically isolate the first well 9 from the substrate 7, like the memory cell 2 it is isolated from the substrate 7 by a buried horizontal layer 8. Both memory cell 2 and driver cell 4 are also isolated laterally from the surrounding p-doped material by a vertical area 11. The buried horizontal layer 8 and the vertical area 11 are both of the second conductivity type, so in this case of type n. The electrodes 12 on the surface of the semiconductor are used to drive the transistors fabricated in the wells or to apply a supply voltage, labeled in the figures as UWL/UBL or UDV, to the transistors.