Method for forming a borderless contact of a semiconductor device
AssigneeHynix Semiconductor Inc.
InventorJun Ho Yoon
Life of this patent
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Abstract
A method for forming a borderless contact of a semiconductor device includes forming a gate electrode on a field oxide of the semiconductor substrate, patterning a stacked structure of a buffer layer and an etching barrier layer on sidewalls of the gate electrode and on the field oxide, forming a silicide layer on the gate electrode and an active region exposed by the stacked structure, and forming the borderless contacts to reduce or prevent leakage current between the semiconductor device and the metal lines and degradation resulting from stresses inherent in the prior art nitride etching barrier layer by reducing abnormal oxidation associated with the buffer oxide layer under the etching barrier layer.
Claims14
A method for forming a borderless contact for a semiconductor device including a field oxide defining an active region, comprising the steps of:
- forming a gate electrode on the field oxide of the semiconductor device;
- forming a stacked structure of a buffer layer pattern and an etching barrier layer pattern on sidewalls of the gate electrode and on the field oxide;
- forming a silicide layer on the surface of the gate electrode and on the active region which are exposed through the stacked structure;
- and
- forming a borderless contact hole.
A method for forming a borderless contact of a semiconductor device, comprising the steps of:
- forming a field oxide defining an active region on a semiconductor substrate;
- forming a gate electrode on the field oxide;
- forming a stacked structure comprising a buffer layer and an etching barrier layer on a whole surface of the semiconductor substrate, including the gate electrode;
- forming a photoresist pattern which exposes the stacked structure on the gate electrode and on an upper surface of the active region;
- anisotropically etching the exposed stacked structure using the photoresist pattern as a mask to expose an upper surface of the gate electrode and the upper surface of the active region, and removing the photoresist pattern;
- forming a silicide layer on the upper surface of the gate electrode and the upper surface of the active region where the stacked structure has been removed;
- forming a first interlayer insulation film on the whole surface;
- forming a second interlayer insulation film on the first interlayer insulation film;
- forming a third interlayer insulation film on the second interlayer insulation film;
- and
- forming a borderless contact hole by selectively etching the third, the second, and the first interlevel insulation layers using a contact etch mask to expose a portion of the gate electrode and a portion of the active region.
Dependencies are inferred from the claim text.