Method for reducing gouging during via formation
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsDaniel Yen, Wei Hua Cheng, Yakub Aliyu, Lee Yuan Ping
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AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsDaniel Yen, Wei Hua Cheng, Yakub Aliyu, Lee Yuan Ping
Estimating the term…
A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target. In this embodiment, liner material residing in the region where the opening is unlanded prevents further gouging of the substrate proximate to the target.
A method for reducing gouging during via formation, said method comprising the steps of:
A method for forming an interconnect with reduced gouging, said method comprising the steps of:
Dependencies are inferred from the claim text.