Method of fabricating copper interconnects with very low-k inter-level insulator

A method of forming a low-k inter-level insulator structure comprising the steps of:

• a) providing a substrate with an initial metal layer thereon;
• b) depositing a passivation insulator overlying the initial metal layer;
• c) depositing a first low-k dielectric layer overlying the passivation insulator;
• d) depositing an etch stop overlying the first low-k dielectric layer;
• e) depositing a sacrificial insulator layer overlying the etch stop;
• f) depositing a hard mask overlying the sacrificial insulator layer;
• g) applying a first photoresist pattern overlying the hard mask and etching via openings in the hard mask;
• h) etching the sacrificial layer where exposed by the via opening until reaching the etch stop, whereby a partial via having a bottom is produced;
• i) applying a second photoresist pattern overlying the hard mask;
• j) etching exposed portions of the hard mask;
• k) etching the etch stop exposed at the bottom of the partial via;
• l) etching the sacrificial layer where it is not covered by the second photoresist pattern, whereby a trench is formed in the sacrificial layer;
• m) etching the first low-k dielectric layer below the bottom of the partial via until the first metal layer is reached, whereby a via is formed;
• n) depositing a second metal layer over the substrate, including all overlying structures, whereby the metal fills the trench and the via to connect with the first metal layer;
• o) polishing the second metal layer until the sacrificial layer is exposed;
• p) removing exposed portions of the sacrificial layer;
• q) depositing a second low-k dielectric layer and back etching to expose the second metal layer, whereby the second low-k dielectric layer replaces the sacrificial layer, which was removed.