Method for forming a fuse in a semiconductor device

A method of forming a fuse pattern comprising:

• a) sequentially forming a barrier metal layer and a metal layer on a substrate having a lower structure formed thereon;
• b) sequentially etching the metal layer and the barrier metal layer in a first region to form a metal wiring pattern and to partially expose the lower structure;
• c) forming an insulating layer continuously on the metal layer and the partially exposed lower structure;
• d) sequentially etching the insulating layer in a second region and the lower structure under the insulating layer by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound to define a fuse pattern region by exposing the metal wiring pattern in the second region, a residue of the insulating layer remaining at a lower portion of a side wall of the metal wiring pattern;
• and
• e) etching the metal layer in the metal wiring pattern of the fuse pattern to form the fuse by exposing a top surface of the barrier metal layer under the metal layer.

A method of forming a fuse pattern comprising:

• a) sequentially forming a barrier metal layer and a metal layer on a substrate having a lower structure formed thereon;
• b) sequentially etching the metal layer and the barrier metal layer in a first region to form a metal wiring pattern and to partially expose the lower structure;
• c) forming an insulating layer continuously on the metal layer and the partially exposed lower structure;
• d) forming a photoresist pattern on the insulating layer to expose the insulating layer in a second region of the insulating layer;
• e) sequentially etching the insulating layer in the second region and the lower structure under the insulating layer by using a first etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound to define a fuse pattern region by exposing the metal wiring pattern in the second region, a residue of the insulating layer remaining at a lower portion of a side wall of the metal wiring pattern;
• f) dry etching a portion of the metal layer in the metal wiring pattern with a second etching gas;
• g) completely removing a photoresist pattern;
• and
• h) wet etching a remaining metal layer, the wet etching having an etching selectivity of the metal layer with respect to the barrier metal layer to form the fuse by exposing a top surface of the barrier metal layer under the metal layer.