US 6,686,247 B1Granted

Self-aligned contacts to gates

AssigneeIntel Corporation

InventorMark Bohr

Life of this patent

Estimating the term…

Loading patent…

Abstract

The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if misaligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.

Claims6

Dependent claims

A method comprising:

forming an active region;
forming a gated device within the active region;
forming a conformal etch stop layer on the junction region and the gate of the gated device;
then
forming a first conformal dielectric layer on the gated device in the active region;
planarizing the first conformal dielectric layer to expose the conformal etch stop layer on a portion of the gate;
forming a second etch stop layer on the first dielectric layer and the conformal etch stop layer;
forming a second dielectric layer on the second etch stop layer;
forming a contact opening through the dielectric layer to a junction region of the gated device using a first mask;
forming a contact opening through the dielectric layer to the gate of the gated device using a different second mask;
wherein the forming a contact opening through the dielectric layer and to the gate further comprises:
etching an initial gated contact opening to the second etch stop layer;
and
etching a subsequent gate contact opening to the gate;
then
forming a contact to a gate of the gated device in the active region.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/226,498Filed 22 Aug 2002
Granted: 3 Feb 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
Y10S 257/903
Active solid-state devices, e.g. transistors, solid-state diodes: fET configuration adapted for use as static memory cell
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by
Y10S
Technical subjects covered by former uspc cross-reference art collections [xracs] and digests